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ARM architecture
Reference Manuals
ARMv5 Architecture Reference Manual
Getting this document
ARMv7-M Application Level Architecture Reference Manual
Getting this document
ARMv7-AR Architecture Reference Manual
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ARMv7-M Architecture Reference Manual
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ARMv6-M Architecture Reference Manual
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Jazelle
Jazelle v1 Architecture Reference Manual
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CoreSight and ETM Architecture Specifications
CoreSight™ Program Flow Trace™ Architecture Specification, v1.0
Preface
About this specification
Product revision status
Intended audience
Using this specification
Conventions
Typographical
Numbering
Further reading
ARM publications
Feedback
Feedback on the Program Flow Trace architecture
Feedback on this specification
Introduction
About the Program Trace Macrocell
Structure of a PTM
The debug environment
Thumb, ThumbEE, and Java support
Connections to a PTM
Trace compression
Resets
Program Flow Tracing
About Program Flow Tracing
Tracing branches
Tracing exceptions
Nonwaypoint instructions
PFT trace example
Waypoint instructions
Unpredictable encodings
Upgrading a nonwaypoint instruction on an exception
Timestamping
Program Trace Macrocell Programmer’s Model
About the PTM programmer’s model
CoreSight support
Programmer’s model requirements
Topology detection requirements
TraceEnable
About TraceEnable
Imprecise TraceEnable events
TraceEnable rules
The TraceEnable start/stop block
TraceEnable Include/exclude control
Address comparators
General behavior of address comparators
Terms used to describe address comparator behavior
Single address comparators (SACs)
Address range comparators (ARCs)
Context ID comparators
EmbeddedICE watchpoint comparator inputs
EmbeddedICE watchpoint comparator input behavior
Default behavior of EmbeddedICE watchpoint comparator inputs
Pulse and latch behavior of EmbeddedICE watchpoint comparator inputs
Examples of using EmbeddedICE watchpoint comparator inputs
Event resources and PTM events
The PTM event resources
Example PTM resource configuration
Defining a PTM event
Examples of event programming
Summary of the PTM events
PTM counters
Use of PTM counters
The PTM sequencer
Use of the PTM sequencer
Instrumentation resources
The Instrumentation resource event resources
Instructions for controlling the Instrumentation resources
Hint field encodings for the DBG Instrumentation instructions
Instrumentation resource behavior when tracing parallel execution
PTM input resources
External inputs
Extended external inputs
Non-secure state resource
Trace prohibited resource
Hard-wired TRUE resource
PTM external outputs
About the PTM registers
Register short names
PTM trace and PTM management registers
Accessing the PTM registers
Coprocessor access
The coprocessor access model
Determination of support
Behavior of other CP14 accesses with Opcode_1 equal to 1
Memory-mapped access
Restrictions on the type of access to PTM registers
PTM register access models
Use of the Programming bit
Programming bit and associated state
PTM state items
Synchronization of PTM register updates
Organization of the PTM registers
PTM register descriptions
Main Control Register, ETMCR
Checking support for implementation defined features
Configuration Code Register, ETMCCR
Trigger Event Register, ETMTRIGGER
Status Register, ETMSR
System Configuration Register, ETMSCR
About the TraceEnable control registers
TraceEnable Start/Stop Control Register, ETMTSSCR
TraceEnable Event Register, ETMTEEVR
TraceEnable Control Register, ETMTECR1
Tracing all memory
FIFOFULL Level Register, ETMFFLR
About the address comparator registers
Address Comparator Value Registers, ETMACVR1 to ETMACVR16
Address Comparator Access Type Registers, ETMACTR1 to ETMACTR16
About the counter registers
Counter Reload Value Registers, ETMCNTRLDVR1 to ETMCNTRLDVR4
Counter Enable Event Registers, ETMCNTENR1 to ETMCNTENR4
Counter Reload Event Registers, ETMCNTRLDEVR1 to ETMCNTRLDEVR4
Counter Value Registers, ETMCNTVR1 to ETMCNTVR4
About the sequencer registers
Sequencer State Transition Event Registers, ETMSQmnEVR
Current Sequencer State Register, ETMSQR
External Output Event Registers, ETMEXTOUTEVR1 to ETMEXTOUTEVR4
About the Context ID comparator registers
Context ID Comparator Value Registers, ETMCIDCVR1 to ETMCIDCVR3
Context ID Comparator Mask Register, ETMCIDCMR
Implementation specific registers, ETMIMPSPEC0 to ETMIMPSPEC7
Implementation specific Register 0, ETMIMPSPEC0
Synchronization Frequency Register, ETMSYNCFR
ID Register, ETMIDR
Configuration Code Extension Register, ETMCCER
Extended External Input Selection Register, ETMEXTINSELR
TraceEnable Start/Stop EmbeddedICE Control Register, ETMTESSEICR
EmbeddedICE Behavior Control Register, ETMEIBCR
Timestamp Event Register, ETMTSEVR
Auxiliary Control Register, ETMAUXCR
CoreSight Trace ID Register, ETMTRACEIDR
About the OS Save and Restore registers
OS Lock Access Register, ETMOSLAR
OS Lock Status Register, ETMOSLSR
OS Save and Restore Register, ETMOSSRR
Device Power-Down Status Register, ETMPDSR
Integration Mode Control Register, ETMITCTRL
About the claim tag registers
Claim Tag Set Register, ETMCLAIMSET
Claim Tag Clear Register, ETMCLAIMCLR
About the lock registers
Lock Access Register, ETMLAR
Lock Status Register, ETMLSR
Authentication Status Register, ETMAUTHSTATUS
Implementation of the Secure non-invasive debug field
Device Configuration Register, ETMDEVID
Device Type Register, ETMDEVTYPE
About the peripheral identification registers
Peripheral ID0 Register, ETMPIDR0
Peripheral ID1 Register, ETMPIDR1
Peripheral ID2 Register, ETMPIDR2
Peripheral ID3 Register, ETMPIDR3
Peripheral ID4 Register, ETMPIDR4
Peripheral ID5 to Peripheral ID7 Registers, ETMPIDR5 to ETMPIDR7
About the component identification registers
Component ID0 Register, ETMCIDR0
Component ID1 Register, ETMCIDR1
Component ID2 Register, ETMCIDR2
Component ID3 Register, ETMCIDR3
Access controls for PTM registers
Access types
Meanings of terms and abbreviations used in this section
Access permissions for memory-mapped accesses
Access permissions for separate core and debug power domains
Access permissions for SinglePower systems
Access permissions for coprocessor accesses
Power-down support
The process of saving and restoring the PTM state
PTM behavior when the OS Lock is set
Guidelines for the PTM trace registers to be saved and restored
Programming the PTM to trace all execution
Program Flow Trace Protocol
About the Program Flow Trace protocol
PFT atoms
Summary of PFT packets
Cycle-accurate tracing
PFT packet formats
A-sync, alignment synchronization packet
I-sync, instruction synchronization packet
The I-sync cycle count field
Periodic and Nonperiodic I-sync packets
Atom packet
Atom packets when cycle-accurate tracing is not enabled
Atom packets when cycle-accurate tracing is enabled
Branch address packet
Branch address packet cycle count information in cycle-accurate mode
Address and cycle count compression in branch address packets
Address compression
Branches to Thumb or ThumbEE state, without exception information byte
Branches to Thumb or ThumbEE state, with exception information byte
Branches to ARM state, without exception information byte
Branches to ARM state, with exception information byte
Cycle count compression
Waypoint update packet
Trigger packet
Context ID packet
Timestamp packet
Exception return packet
Ignore packet
Branch broadcasting
Prohibited regions
Behavior of the PTM when the processor is in a prohibited region
Trace FIFO overflow
Wait for Interrupt and Wait for Event
Large blocks of instructions
Synchronization
Periodic synchronization
Forced overflow
Alignment synchronization
Instruction synchronization
Nonperiodic I-sync
Periodic I-sync
Timestamp synchronization
Tracing security state changes
Changing from Non-secure to Secure state
Changing from Secure to Non-secure state
Use of a return stack
Timestamping
Trace flushing
CoreSight or other ATB flush request
Setting the Programming bit or the OS Lock
WFI or WFE request
Non-invasive debug disabled
Tracing Thumb instructions
32-bit Thumb instructions
Thumb CBZ and CBNZ instructions
Jazelle state
Debug state
Tracing Exceptions
About exception tracing in the PFT architecture
The different exception cases
Exception occurs after a nonwaypoint instruction
Exception occurs immediately after a waypoint instruction
Exception occurs immediately after another exception
Exceptions occurring close together but not back-to-back
Turning trace on between two back-to-back exceptions
Exception occurs immediately after trace turn-on
Exception occurs before execution of instruction at the I-sync target address
Exception occurs after execution of instruction at the I-sync target address
Tracing the different exception types
Processor reset exception
Undefined Instruction exception
SVC (Supervisor Call) or SMC (Secure Monitor Call) exception
Prefetch Abort exception
Synchronous Data Abort exception
Asynchronous Data Abort, FIQ or IRQ exception
Debug state entry, when Halting debug-mode is enabled
Tracing exit from Debug state
ThumbEE check that goes to a handler, including the CHKA instruction
Jazelle exception that goes to an ARM or Thumb state handler
Secure to Non-secure state change
Other exceptions
Waypoint update addresses
PTM Quick Reference Information
PTM event resources
Resource identification and event encoding
Resource control registers
Summary of implementation defined PTM features
Trace Decompressor Operation
About PTM trace decompression
PFT trace state and objects
PFT state information
PFT output objects
PFT trace decompression flow
Overall PFT trace decompression flow
Details of PFT trace decompression operations
branch_no_excp()
branch_with_excp()
analyze_atomheader()
analyze_cid()
analyze_waypoint_update()
decode_instr()
Software Issues for PFT
About tracing dynamically-loaded code
Simple overlay support
Software support for Context ID
Hardware support for Context ID
Glossary
High Speed Serial Trace Port Architecture Specification
Getting this document
CoreSight Architecture Specification Rev 1.0
Getting this document
Embedded Trace Macrocell Architecture Specification
Preface
About this specification
Product revision status
Intended audience
Using this specification
Conventions
Typographical
Numbering
Further reading
The ETM documentation suite
Other ARM publications
Feedback
Feedback on the Embedded Trace Macrocell
Feedback on this specification
Introduction
About Embedded Trace Macrocells
Structure of an ETM
The debug environment
Thumb and Java support
Trace compression
ETM versions and variants
Controlling Tracing
About controlling tracing
ETM event resources
Memory access resources
Single address comparators
Address range comparators
No data address comparator option, ETMv3.3 and later
Data value comparators
Context ID comparators
EmbeddedICE watchpoint comparators
Memory map decoder (MMD)
Instrumentation resources, ETMv3.3 and later
Derived resources
Counters
Sequencer
Trace start/stop resource
External inputs
Hard-wired input
External inputs
Extended external input selectors
Non-secure state resource
Prohibited region resource
Example resource configuration
ETM event logic
Triggering a trace run
External outputs
Trace filtering
Definitions of when an ETM is tracing
Behavior while tracing is prohibited
Programming strategies
TraceEnable and filtering the instruction trace
Data-controlled instruction tracing
Imprecise TraceEnable events
Rules for the transition of TraceEnable
The trace start/stop block
Using the trace start/stop block to control TraceEnable
ViewData and filtering the data trace
Imprecise ViewData events
Setting start and stop conditions
Filter Coprocessor Register Transfers (CPRT) in ETMv3.0 and later
Operation of ViewData
ViewData operation examples for Exclude mode
ViewData operation examples for Mixed mode
Restrictions on ViewData programming
Preventing FIFO overflow
Processor stalling, FIFOFULL
Data suppression
Checking whether data suppression is supported, ETMv3.3 and later
Restriction if FIFOFULL and data suppression are both implemented
Address comparators
Comparator access size
Comparator access size field behavior, in ETMv3.1 and later
Single address comparators configured for data addresses
Single address comparators configured for instruction addresses
Address range comparators configured for data addresses
Address range comparators configured for instruction addresses
Comparator access size field behavior, in ETMv3.0 and earlier
Address range comparison behavior of ETMv3.0 and earlier
Exact matching, ETMv2.0 and later
Exact matching for instruction address comparisons
Exact matching for data address comparisons
Additional details of the effect of the Exact match bit
Exact matching, ETMv1.x
Behavior of address comparators
Access types for address range comparators
Selecting a range to include address 0xFFFFFFFF
Comparator precision
Coprocessor transfers
Comparator configuration example
Operation of the comparators
Programming the comparator registers for this example
Operation of data value comparators
Terms used in this section
Operation of data value comparators, ETMv3.2 and earlier
Operation of data value comparators, ETMv3.3 and later
Data value matching with single address comparators
Constraints and rules for data value matching with single address comparators
Data value matching with address range comparators
Address matching of an address range comparator
Data value matching of an address range comparator
Constraints and rules for data value matching with address range comparators
Summary of alignment and endianness considerations for different ETM versions
Instrumentation resources, from ETMv3.3
The Instrumentation resource event resources
Instructions for controlling the Instrumentation resources
Hint field encodings for the DBG instrumentation instructions
Instrumentation resource behavior when tracing parallel execution
Trace port clocking modes
ETMv1 and ETMv2 behavior
ETMv3 behavior
Considerations for advanced cores, ETMv2 and later only
Parallel execution
Rules for parallel execution
Independent load/store unit
Consequences of parallel execution on counters
Consequences of parallel execution on the sequencer
Supported standard configurations in ETMv1
Choosing a configuration
ETM7 supported configurations
ETM9 supported configurations
Supported configurations from ETMv2
Behavior when non-invasive debug is disabled
Programmer’s Model
About the programmer’s model
Programming and reading ETM registers
JTAG access
Restricting JTAG access
Coprocessor access, ETMv3.1 and later
Coprocessor models
Limited register set model, ETMv3.1 and ETMv3.2 only
Full access model, ETMv3.3 and later
Behavior of coprocessor accesses
Restricting coprocessor access
Determination of support
Behavior of other CP14 accesses with Opcode_1 equal to 1
ETMv3.1 and v3.2
ETMv3.3 and later
Memory-mapped access, ETMv3.2 and later
Restrictions on the type of access to ETM registers
ETM register access models
Synchronization of ETM register updates
CoreSight support
Programmer’s model requirements
Topology detection requirements
The ETM registers
ETM Trace and ETM Management registers, from ETMv3.3
Reset behavior
Use of the Programming bit
ETM Programming bit and associated state
ETM state items
ETMv3.0 and earlier
ETMv3.1 and later
Detailed register descriptions
ETM Control Register
Additional information on the ETM Control Register
ETM port size encoding
Restrictions on the use of the ETMEN signal
Checking for implementation defined features, from ETMv3.3
Checking support for cycle-accurate tracing, ETMv3.3 and later
Checking which data tracing options are available, ETMv3.3 and later
ETM Configuration Code Register
Trigger Event Register
ASIC Control Register
ETM Status Register, ETMv1.1 and later
System Configuration Register, ETMv1.2 and later
TraceEnable registers
Trace Start/Stop Resource Control Register, ETMv1.2 and later
TraceEnable Control Registers
TraceEnable Control 2 Register, ETMv1.2 and higher
TraceEnable Control 1 Register
TraceEnable Event Register
Tracing all memory
FIFO overflow registers (FIFOFULL control)
FIFOFULL Region Register
FIFOFULL Level Register
ViewData registers
ViewData Event Register
ViewData Control Registers
ViewData Control 1 Register
ViewData Control 2 Register
ViewData Control 3 Register
Programming the ViewData logic
Address comparator registers
Address Comparator Value Registers
Address Access Type Registers
Access types for address range comparators
Selecting a range to include address 0xFFFFFFFF
Data value comparator registers
Data value comparator value registers
Data value comparator mask registers
Alignment considerations
Associating data value comparators with address comparators
Counter registers
Counter Reload Value Registers
Counter Enable Registers
Counter Reload Event Registers
Counter Value Registers
Sequencer registers
Sequencer State Transition Event Registers
Current Sequencer State Register
External Output Event Registers
Context ID comparator registers, ETMv2.0 and later
Context ID Comparator Value Registers
Context ID Comparator Mask Register
implementation specific registers
implementation specific Register 0
Synchronization Frequency Register, ETMv2.0 and later
Finding the access type, ETMv3.4 and later
ETM ID Register, ETMv2.0 and later
The ETM architecture version
The Core family field
Configuration Code Extension Register, ETMv3.1 and later
Extended External Input Selection Register, ETMv3.1 and later
Trace Start/Stop EmbeddedICE Control Register, ETMv3.4 and later
EmbeddedICE Behavior Control Register, ETMv3.4 and later
CoreSight Trace ID Register, ETMv3.2 and later
Operating System Save and Restore Registers, ETMv3.3 and later
OS Lock Access Register (OSLAR), ETMv3.3 and later
OS Lock Status Register (OSLSR), ETMv3.3 and later
OS Save and Restore Register (OSSRR), ETMv3.3 and later
Device Power-Down Status Register (PDSR)
Integration Mode Control Register (ITCTRL), ETMv3.2 and later
Claim tag registers, ETMv3.2 and later
Claim Tag Set Register (CLAIMSET)
Claim Tag Clear Register (CLAIMCLR)
Lock registers, ETMv3.2 and later
Lock Access Register (LAR or LOCKACCESS)
Lock Status Register (LSR or LOCKSTATUS)
Authentication Status Register (AUTHSTATUS), ETMv3.2 and later
Implementation of the Secure non-invasive debug field
Device Configuration Register (DEVID), ETMv3.2 and later
Device Type Register (DEVTYPE), ETMv3.2 and later
Peripheral identification registers, ETMv3.2 and later
Peripheral ID0 Register
Peripheral ID1 Register
Peripheral ID2 Register
Peripheral ID3 Register
Peripheral ID4 Register
Peripheral ID5 to Peripheral ID7 Registers
Component identification registers, ETMv3.2 and later
Component ID0 Register
Component ID1 Register
Component ID2 Register
Component ID3 Register
Using ETM event resources
Resource identification
Resource encoding
Boolean combinations for defining events
Where are events used?
Defining events
Examples of event and resource programming
Example ViewData and TraceEnable configurations
An example ViewData configuration
An example TraceEnable configuration
Power-down support, ETMv3.3 and later
The process of saving and restoring the macrocell ETM state
ETM behavior when the OS Lock is set
Guidelines for the ETM trace registers to be saved and restored
Access permissions for ETM registers
Access types
Meanings of terms and abbreviations used in this section
Restrictions on accesses using a direct JTAG connection
Access permissions for memory-mapped accesses
Access permissions for separate core and debug power domains
Access permissions for SinglePower systems
Access permissions for coprocessor accesses
Signal Protocol Overview
About trace information
Signal protocol variants
Structure of the trace port
Signals
ETMv1.x and ETMv2.x signals
ETMv3.x signals
Multiplexed trace port (ETMv1.x and ETMv2.x only)
Demultiplexed trace port (ETMv1.x and ETMv2.x only)
ETM structures
ETMv1.x
ETMv2.x
ETMv3.x
Decoding required by trace capture devices
Trigger conditions
Trace disabled conditions
Storage of TRACECTL
Instruction trace
Instruction trace filtering
Direct and indirect branches
Exceptions
Jazelle and ThumbEE exceptions
32-bit Thumb instructions
Thumb CBZ and CBNZ instructions
Data trace
Data access filtering
Address and data selection
Preloads
Asynchronous data aborts
Context ID tracing
Debug state
Endian effects and unaligned access
Summary of ARM behavior
Representation of data in the trace
Definitions
Load/Store Multiple (LSM) instructions
Data Instructions
Direct branch instructions
Coprocessor operations
Coprocessor data operation
Coprocessor data transfer
ETMv1
Coprocessor register transfer
Wait For Interrupt and Wait For Event
ETMv1 Signal Protocol
ETMv1 pipeline status signals
Trigger PIPESTAT signals
ETMv1 trace packets
Rules for generating and analyzing the trace in ETMv1
Additional considerations for 16-bit ports
Example ETMv1 trace
Pipeline status and trace packet association in ETMv1
Instruction tracing in ETMv1
Direct branches to the exception vector table
ARM and Thumb code
Java code
Compressed branch address packet structure
Moving to and from Jazelle state (ETMv1.3 only)
Branch reason codes
Trace synchronization in ETMv1
Address Packet Offset
Full address output
Context ID tracing
Data tracing in ETMv1
PIPESTAT signals indicating data accesses in the pipeline
Load/Store Multiple instructions
Trace packet sequence for data accesses
Data aborts
Address compression performed by the ETM
Filtering the ETMv1 trace
Enabling trace
Disabling trace
Data accesses during disabled trace
Precise events
FIFO overflow
System stalling
Cycle-accurate tracing
Tracing Java code, ETMv1.3 only
ETMv2 Signal Protocol
ETMv2 pipeline status signals
Wait PIPESTAT signals
Branch phantom PIPESTAT signals
Data PIPESTAT signals
Instruction Executed PIPESTAT signals
Instruction Not Executed PIPESTAT signals
TD PIPESTAT signals
Trigger PIPESTAT signals
ETMv2 trace packets
Rules for generating and analyzing the trace in ETMv2
Trace packet types
Trace packet headers
Normal Data packets
64-bit data transfers
Load Miss packets
Load Miss Occurred
Load Miss Data
Out-of-order miss data
Rules for generation of Load Miss trace packets
64-bit loads
Value Not Traced packets
Context ID packets
Trace synchronization in ETMv2
Trace FIFO offsets
TFO values
TFO formula
General TFO packet structure
Trigger considerations
Mid-byte TFO outputs
TFO packet types
TFO packet headers
Normal TFO packets
TFO reason codes
LSM In Progress TFO packets
Data address synchronization
Context ID tracing
Tracing through regions with no code image
Instruction tracing with ETMv2
Branch Address trace packets
Branch address generation
Exception branch addresses
Full branch address reason codes
Data tracing in ETMv2
Data aborts
Imprecise data aborts, ETMv2.1 and later
Decoding the data trace packets
Address compression performed by the ETM
Filtering the ETMv2 trace
Enabling trace
Disabling trace
Data accesses during disabled trace
FIFO overflow
Cycle-accurate tracing
ETMv3 Signal Protocol
Introduction
Packet types
Instruction tracing
P-headers
Generation
P-header encodings in non cycle-accurate mode
P-header encodings in cycle-accurate mode
The cycle-accurate mode format 4 P-header, ETMv3.3 and later
Condition codes on canceled and undefined instructions
Cycle information, for cycle-accurate tracing
Cycle count packet
Branch packets
Branch packets summary
Branch packet formats with the original address compression scheme
Tracing branches with exceptions, original scheme
Branch address compression, original scheme
Branch packet formats with the alternative address compression scheme
Overall branch packet format in the alternative address compression scheme
Normal (no exception) branch packets in the alternative encoding
Exception branch packets in the alternative encoding
Exception branch addresses packets
The AltISA bit, ETMv3.3 and later
Encoding of Exception[3:0], for core architectures other than ARMv7-M
Missing components of exception Branch address packets
Branch address packets for change of security state
Branch address packets for change of processor state
Changes of state that are not indicated explicitly
Extended exception handling, from ETMv3.4
Possible forms of the Exception information section
Extended exception handling in Instruction-only trace
Branch address generation
Context ID packets
Data tracing
Data packet types
Normal data packet
The A bit
BE bit
Size bits
Out-of-order packets
Out-of-order placeholder
The A bit
Tag bits
BE bit
Out-of-order data
Rules for generation of Out-of-order packets
64-bit values
Tracing LSMs
Value not traced packet
Data suppressed packet
Store failed packet
Jazelle data tracing
Data aborts
Asynchronous data aborts
Data-only mode, ETMv3.1 and later
Tracing LSM instructions in data-only mode
Possible wrong interpretation of CPRT trace in data-only mode
Data tracing options, ETMv3.3 and later
Detecting which data tracing options are available
Exceptions on Data Instructions
Additional trace features for ARMv7‑M cores, from ETMv3.4
Support for a large number of exceptions
Instructions that can be paused for continuation
Tracing continuation of an instruction during instruction-only trace
Automatic stack push on exception entry and pop on exception exit
Tracing return from an exception
Data tracing of return from exception
Behavior of EmbeddedICE inputs, from ETMv3.4
EmbeddedICE watchpoint comparator input behavior
Default behavior of EmbeddedICE watchpoint inputs
Implementation of pulse and latch behavior of EmbeddedICE inputs
EmbeddedICE input usage examples
Synchronization
Frequency of synchronization
A-sync, alignment synchronization
I-sync instruction synchronization
Use of I-sync packets in cycle-accurate mode
Normal I-sync packet
The Alternative instruction set bit, ETMv3.3 and later
Normal I-sync with cycle count packet
Load/Store in Progress (LSiP) I-sync packet
Load/Store in Progress (LSiP) I-sync with cycle count packet
Data-only I-sync packet
Reason codes
D-sync, data address synchronization
Trace port interface
Trigger
Ignore
FIFO draining
Tracing through regions with no code image
Cycle-accurate tracing
Tracing long gaps in cycle-accurate trace
Support for cycle-accurate tracing, ETMv3.3 and later
ETMv2 and ETMv3 compared
ETMv2 PIPESTAT encodings and ETMv3 P-headers compared
ETMv2 TFO packets and ETMv3 I-sync packets compared
Trace Port Physical Interface
Target system connector
Target connector pinouts
Assignment of trace information pins between ETM architecture versions
Single target connector pinout
Pipeline status seen by old TPAs, ETMv3.0 upwards
Wider trace ports, ETMv3.0 upwards
Dual target connector pinout
Asynchronous trace ports
Synchronous trace ports
Multiplexed trace port, single target connector pinout (ETMv1.x and ETMv2.x)
Demultiplexed trace port target connector pinout
Signal descriptions
EXTTRIG input
VTRef output
VSupply output
nTRST input
TDI input
TMS input
TCK input
RTCK output
TDO output
nSRST input
DBGRQ input
DBGACK output
VDD input
Connector placement
Connector orientation
Dual connector placement
Timing specifications
Half-rate clocking mode
Signal level specifications
Other target requirements
JTAG control connector
Tracing Dynamically Loaded Images
About tracing dynamically-loaded code
Simple overlay support