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ARM architecture
Reference Manuals
ARMv5 Architecture Reference Manual
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ARMv7-M Application Level Architecture Reference Manual
Getting this document
Other ARM Architecture Reference Manuals
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Jazelle
Jazelle v1 Architecture Reference Manual
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Other Specifications
ARM Debug Interface v5
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Cortex processors
Cortex-A8
Revision: r2p2
Cortex™-A8 Technical Reference Manual
Preface
About this manual
Product revision status
Intended audience
Using this manual
Conventions
Typographical
Timing diagrams
Signals
Numbering
Additional reading
ARM publications
Other publications
Feedback
Feedback on the product
Feedback on this manual
Introduction
About the processor
ARMv7-A architecture
Components of the processor
Instruction fetch
Instruction decode
Instruction execute
Load/store
L2 cache
NEON
ETM
External interfaces of the processor
AMBA AXI interface
AMBA APB interface
AMBA ATB interface
DFT interface
Debug
Power management
Configurable options
Product revisions
Programmer’s Model
About the programmer’s model
Thumb-2 instruction set
ThumbEE instruction set
Instructions
Configuration
ThumbEE Configuration Register
ThumbEE HandlerBase Register
Access to ThumbEE registers
Jazelle Extension
Jazelle Identity Register
Jazelle Main Configuration Register
Jazelle OS Control Register
Security Extensions architecture
Security Extensions model
Advanced SIMD architecture
VFPv3 architecture
Processor operating states
Switching state
Interworking ARM and Thumb state
Data types
Memory formats
Byte-invariant big-endian format
Little-endian format
Addresses in a processor system
Operating modes
Registers
The state register set
The program status registers
The condition code flags
The Q flag
The IT execution state bits
The J bit
The GE[3:0] bits
The E bit
The A bit
The control bits
Interrupt disable bits
T bit
Mode bits
Modification of PSR bits by MSR instructions
Reserved bits
Exceptions
Exception entry and exit summary
Leaving an exception
Reset
Fast interrupt request
Interrupt request
Aborts
Prefetch abort
Data abort
Precise data aborts
Imprecise data aborts
Imprecise data abort mask in the CPSR/SPSR
Software interrupt instruction
Software Monitor Instruction
Undefined instruction
Breakpoint instruction
Exception vectors
Exception priorities
Software consideration for Security Extensions
Hardware consideration for Security Extensions
System boot sequence
Security Extensions write access disable
Secure monitor bus
SECMONOUT protocol
Control coprocessor
System Control Coprocessor
About the system control coprocessor
System control coprocessor functional groups
System control and configuration
Security Extensions write access disable
MMU control and configuration
Cache control and configuration
L2 cache preload engine control and configuration
System performance monitor
Array debug
System control coprocessor registers
Register allocation
c0, Main ID Register
c0, Cache Type Register
c0, TCM Type Register
c0, TLB Type Register
c0, Multiprocessor ID Register
c0, Processor Feature Register 0
c0, Processor Feature Register 1
c0, Debug Feature Register 0
c0, Auxiliary Feature Register 0
c0, Memory Model Feature Register 0
c0, Memory Model Feature Register 1
c0, Memory Model Feature Register 2
c0, Memory Model Feature Register 3
c0, Instruction Set Attributes Register 0
c0, Instruction Set Attributes Register 1
c0, Instruction Set Attributes Register 2
c0, Instruction Set Attributes Register 3
c0, Instruction Set Attributes Register 4
c0, Instruction Set Attributes Registers 5-7
c0, Cache Level ID Register
c0, Silicon ID Register
c0, Cache Size Identification Registers
c0, Cache Size Selection Register
c1, Control Register
c1, Auxiliary Control Register
c1, Coprocessor Access Control Register
c1, Secure Configuration Register
c1, Secure Debug Enable Register
c1, Nonsecure Access Control Register
c2, Translation Table Base Register 0
c2, Translation Table Base Register 1
c2, Translation Table Base Control Register
c3, Domain Access Control Register
c5, Data Fault Status Register
c5, Instruction Fault Status Register
c5, Auxiliary Fault Status Registers
c6, Data Fault Address Register
c6, Instruction Fault Address Register
c7, cache operations
Data formats for the cache operations
Set and way
MVA
SBZ
VA to PA translation operations
PA Register
VA to PA translation in the current Secure or Nonsecure state
VA to PA translation in the other Secure or Nonsecure state
Data synchronization barrier operation
Data memory barrier operation
c8, TLB operations
Invalidate TLB unlocked entries
Invalidate TLB Entry by MVA
Invalidate TLB Entry on ASID Match
c9, Performance Monitor Control Register
c9, Count Enable Set Register
c9, Count Enable Clear Register
c9, Overflow Flag Status Register
c9, Software Increment Register
c9, Performance Counter Selection Register
c9, Cycle Count Register
c9, Event Selection Register
c9, Performance Monitor Count Registers
c9, User Enable Register
c9, Interrupt Enable Set Register
c9, Interrupt Enable Clear Register
c9, L2 Cache Lockdown Register
Specific loading of addresses into cache way
Cache unlock procedure
c9, L2 Cache Auxiliary Control Register
c10, TLB Lockdown Registers
c10, TLB preload operation
c10, Memory Region Remap Registers
c11, PLE Identification and Status Registers
c11, PLE User Accessibility Register
c11, PLE Channel Number Register
c11, PLE enable commands
c11, PLE Control Register
c11, PLE Internal Start Address Register
c11, PLE Internal End Address Register
c11, PLE Channel Status Register
c11, PLE Context ID Register
c12, Secure or Nonsecure Vector Base Address Register
c12, Monitor Vector Base Address Register
c12, Interrupt Status Register
c13, FCSE PID Register
c13, Context ID Register
c13, Thread and Process ID Registers
c15, L1 system array debug data registers
c15, L1 TLB operations
TLB CAM array examples
TLB ATTR array examples
TLB PA array examples
c15, L1 HVAB array operations
c15, L1 tag array operations
c15, L1 data array operations
c15, BTB array operations
c15, GHB array operations
c15, L2 system array debug data registers
c15, L2 parity/ECC array operations
c15, L2 tag array operations
c15, L2 data array operations
Unaligned Data and Mixed-endian Data Support
About unaligned and mixed-endian data
Unaligned data access support
NEON data alignment
Alignment specifiers
Normal memory
Device memory and strongly ordered memory
Mixed-endian access support
Program Flow Prediction
About program flow prediction
Predicted instructions
Return stack predictions
Nonpredicted instructions
Guidelines for optimal performance
Enabling program flow prediction
Operating system and predictor context
Instruction memory barriers
Memory Management Unit
About the MMU
Memory access sequence
TLB match process
16MB supersection support
MMU interaction with memory system
External aborts
External aborts on data read or write
Precise and imprecise aborts
TLB lockdown
MMU software-accessible registers
Level 1 Memory System
About the L1 memory system
Cache organization
Cache control operations
Cache miss handling
Cache disabled behavior
Unexpected hit behavior
Cache parity error detection
Instruction cache data RAM parity error detection
Data cache data RAM parity error detection
Memory attributes
Strongly ordered
Device
Normal
Cache debug
Data cache features
Data cache preload instruction
Data cache behavior with C-bit disabled
Instruction cache features
Instruction cache preload instruction
Instruction cache speculative memory accesses
Instruction cache disabled behavior
Hardware support for virtual aliasing conditions
Parity detection
Level 2 Memory System
About the L2 memory system
Cache organization
L2 cache bank structure
L2 cache transfer policy
Enabling and disabling the L2 cache controller
L2 PLE
Configuring the preload engine
Preload engine commands and status interaction
Interaction of the preload engine with WFI
Memory region interaction with the preload engine
Processor configuration and the impact on the preload engine
Effects of cache maintenance operations during preloading engine transfers
Synchronization primitives
Load-exclusive instruction
Store-exclusive instruction
Example of LDREX and STREX usage
Locked access
Parity and error correction code
External Memory Interface
About the external memory interface
External interface servicing instruction fetch transactions
External interface servicing data transactions
AXI control signals in the processor
AXI identifiers
Read/write data bus width configuration pin
AXI instruction transactions
AXI instruction address transactions
AXI data read/write transactions
Linefills
Evictions
NEON accesses to strongly ordered and device memory
AXI data address transactions
Clock, Reset, and Power Control
Clock domains
AXI clocking using ACLKEN
Debug clocking using PCLKEN
ATB clocking using ATCLKEN
Reset domains
Power-on reset
Soft reset
APB and ATB reset
Hardware RAM array reset
Reset of memory arrays
Power control
Dynamic power management
Wait-For-Interrupt architecture
Hardware clock stopping
NEON or ETM unit level gating
DFF gating
Static or leakage power management
NEON power domain
Powering down the NEON power domain while the processor is in reset
Powering down the NEON power domain while the processor is not in reset
Powering up the NEON power domain while the processor is in reset
Powering up the NEON power domain while the processor is not in reset
Debug and ETM power domains
Powering down the debug and ETM power domains
Powering up the debug and ETM domains
Debugging the processor while powered down
Powering down the integer core power domain
Powering up the integer core and NEON power domains
Powering up the integer core power domain while keeping NEON powered down
L1 data and L2 cache power domains
Power cycle the core with L2 cache retaining state
Power cycle the core with L1 data cache and L2 cache retaining state
Special note on reset during power transition
Design for Test
MBIST
About MBIST
MBIST registers
L1 MBIST Instruction Register
pttn[5:0]
rtfail
bitmap
dseed[3:0]
L1_array_sel[22:0]
L1_config[14:0]
L1_ADDR_SCRAMBLE[183:0]
L2 MBIST Instruction Register
L2_ram_sel[4:0]
L2_config[22:0]
L2DLat[3:0]
L2TLat[1:0]
L2Rows[11:0]
L2ValSer
L2AdLSB[3:0]
L2_ADDR_SCRAMBLE[289:0]
L1 and L2 MBIST GO-NOGO Instruction Registers
L1 MBIST Datalog Register
ArrayFail[22:0]
expect_data[3:0]
fail_addr[16:2]
failing_bits[37:0]
alg_pass[3:0]
pattern[5:0]
L2 MBIST Datalog Register
failing_ram[4:0]
expect_data[3:0]
fail_addr[16:0]
read_mux
failing_bits[32:0]
alg_pass[3:0]
pattern[5:0]
MBIST operation
Manufacturing test mode
Bitmap test mode
MBIST Instruction load
MBIST custom GO-NOGO instruction load
Test execution
End-of-test datalog retrieval
Bitmap datalog retrieval
Pattern selection
CAMBIST
CKBD
COLBAR
ROWBAR
SOLIDS
RWXMARCH
RWYMARCH
RWRXMARCH
RWRYMARCH
XMARCHC
YMARCHC
XADDRBAR
YADDRBAR
WRITEBANG
READBANG
FAIL
ADDRESS DECODER
GO-NOGO
ATPG test features
Wrapper
Enabling sections of the core
Reset handling
Safe shift RAM signals
Debug
Debug systems
Debug host
Protocol converter
Debug target
About the debug unit
Halting debug-mode debugging
Monitor debug-mode debugging
Security extensions and debug
Programming the debug unit
Debug register interface
Coprocessor registers
CP14 access permissions
Coprocessor registers summary
Memory-mapped registers
Memory addresses for breakpoints and watchpoints
Power domains and debug
Effects of resets on debug registers
APB interface access permissions
Privilege of memory access permission
Locks permission
Power down permission
Accesses to ETM and CTI registers
Debug register descriptions
Accessing debug registers
CP14 c0, Debug ID Register
CP14 c0, Debug ROM Address Register
CP14 c0, Debug Self Address Offset Register
CP14 c1, Debug Status and Control Register
DTR access mode
Data Transfer Register
Watchpoint Fault Address Register
Vector Catch Register
Event Catch Register
Debug State Cache Control Register
Instruction Transfer Register
Debug Run Control Register
Breakpoint Value Registers
Breakpoint Control Registers
Watchpoint Value Registers
Watchpoint Control Registers
Operating System Lock Access Register
Operating System Lock Status Register
Operating System Save and Restore Register
Device Power Down and Reset Control Register
Device Power Down and Reset Status Register
Management registers
Processor ID Registers
Integration Internal Output Control Register
Integration External Output Control Register
Integration Input Status Register
Integration Mode Control Register
Claim Tag Set Register
Claim Tag Clear Register
Lock Access Register
Lock Status Register
Authentication Status Register
Device Type Register
Identification Registers
Debug events
Software debug event
Halting debug event
Behavior of the processor on debug events
Debug event priority
Watchpoint debug events
Debug exception
Effect of debug exceptions on CP15 registers and WFAR
Avoiding unrecoverable states
Debug state
Entering debug state
Behavior of the PC and CPSR in debug state
Executing instructions in debug state
Writing to the CPSR in debug state
Privilege
Accessing registers and memory
Updating CPSR bits
Writing to the CPSR SCR
Coprocessor instructions
Effect of debug state on noninvasive debug
Effects of debug events on registers
Exceptions in debug state
Imprecise Data Aborts on entry and exit from debug state
Imprecise Data Aborts and watchpoints
Leaving debug state
Cache debug
Cache pollution in debug state
Cache coherency in debug state
Cache usage profiling
External debug interface
Miscellaneous debug signals
EDBGRQ
DBGACK
COMMRX and COMMTX
DBGNOPWRDWN
DBGPWRDWNREQ
DBGPWRDWNACK
DBGOSLOCKINIT
DBGROMADDR
DBGSELFADDR
Authentication signals
Changing the authentication signals
Using the debug functionality
Debug communications channel
Rules for accessing the DCC
Software access to the DCC
Debugger access to the DCC
Programming breakpoints and watchpoints
Programming simple breakpoints and the byte address select
Setting a simple aligned watchpoint
Setting a simple unaligned watchpoint
Single-stepping
Debug state entry
Debug state exit
Accessing registers and memory in debug state
Reading and writing registers through the DCC
Reading the PC in debug state
Reading the CPSR in debug state
Writing the CPSR in debug state
Reading memory
Fast register read/write
Fast memory read/write
Accessing secure and nonsecure coprocessor registers
Debugging systems with energy management capabilities
Standby
Emulating power down
Detecting power down
Operating system support
Registers available during power down
Scenarios and usage models
NEON and VFP Programmer’s Model
About the NEON and VFP programmer’s model
NEON media coprocessor
VFP coprocessor
General-purpose registers
NEON views of the register bank
VFP views of the register bank
Short vectors
About register banks
Operations using register banks
Scalar-only instructions
Short vector-only instructions
Short vector instructions with scalar source
Scalar instructions in short vector mode
System registers
Floating-Point System ID Register, FPSID
Floating-Point Status and Control Register, FPSCR
Vector length and stride control
Floating-point exception Register, FPEXC
Media and VFP Feature Registers, MVFR0 and MVFR1
Modes of operation
Full-compliance mode
Flush-to-zero mode
Default NaN mode
RunFast mode
Compliance with the IEEE 754 standard
Complete implementation of the IEEE 754 standard
IEEE 754 standard implementation choices
NaN handling
Comparisons
Underflow
Exceptions
Embedded Trace Macrocell
About the ETM
ETM features
The debug environment
NEON
ETM configuration
ETM register summary
ETM register descriptions
ID Register
Configuration Code Register
Configuration Code Extension Register
Peripheral Identification Registers
Component Identification Registers
Integration Test Registers
Using the Integration Test Registers
ITMISCOUT Register
ITMISCIN Register
ITTRIGGER Register
ITATBDATA0 Register
ITATBCTR2 Register
ITATBCTR1 Register
ITATBCTR0 Register
Precision of TraceEnable and ViewData
TraceEnable
ViewData
Enabling events
Address comparators
Exact match bit
Address comparators configured for instruction addresses
Address comparators configured for data addresses
Address range comparators
Context ID tracing
Instrumentation instructions
Idle state control
Interaction with the Performance Monitoring Unit
Use of PMU events by the ETM
Use of ETM events by the PMU
Cross Trigger Interface
About the CTI
How the CTI works
The channel interface
Trigger signal synchronization
Trigger inputs and outputs
Connecting asynchronous channel interfaces
About the CTI programmer’s model
CTI register summary
CTI register descriptions
CTI Control Register, CTICONTROL
CTI Interrupt Acknowledge Register, CTIINTACK
CTI Application Trigger Set Register, CTIAPPSET
CTI Application Trigger Clear Register, CTIAPPCLEAR
CTI Application Pulse Register, CTIAPPPULSE
CTI Trigger to Channel Enable Registers, CTIINEN0-8
CTI Channel to Trigger Enable Registers, CTIOUTEN0-8
CTI Trigger In Status Register, CTITRIGINSTATUS
CTI Trigger Out Status Register, CTITRIGOUTSTATUS
CTI Channel In Status Register, CTICHINSTATUS
CTI Channel Gate Register, CTICHGATE
ASIC Control Register, ASICCTL
CTI Channel Out Status Register, CTICHOUTSTATUS
CTI Integration Test Registers
ITTRIGINACK, 0xEE0
ITCHOUT, 0xEE4
ITTRIGOUT, 0xEE8
ITTRIGOUTACK, 0xEF0
ITCHIN, 0xEF4
ITTRIGIN, 0xEF8
CTI CoreSight defined registers
Authentication Status Register, 0xFB8
Device ID Register, 0xFC8
Device Type Identifier, 0xFCC
Peripheral Identification Registers
Component Identification Registers
Instruction Cycle Timing
About instruction cycle timing
Instruction-specific scheduling for ARM instructions
Example of how to read ARM instruction tables
Data-processing instructions
Multiply instructions
Parallel arithmetic and DSP instructions
Extended instructions
Miscellaneous data-processing instructions
Status register access instructions
Load/store instructions
Load multiple and store multiple instructions
Branch instructions
Conditional branches
Branches with the PC as a source or destination
Data processing-based branches
Load-based branches
Coprocessor instructions
Dual-instruction issue restrictions
Other pipeline-dependent latencies
Cycle penalty for instruction flow change
Memory system effects on instruction timings
Thumb-2 instructions
ThumbEE instructions
ThumbEE memory check exceptions
Predicting ThumbEE branch type instructions
Conditional instructions
Advanced SIMD instruction scheduling
Mixed ARM and Advanced SIMD instruction sequences
Passing data between ARM and NEON
Dual issue for Advanced SIMD instructions
Instruction-specific scheduling for Advanced SIMD instructions
Example of how to read Advanced SIMD instruction tables
Advanced SIMD integer ALU instructions
Advanced SIMD integer multiply instructions
Advanced SIMD integer shift instructions
Advanced SIMD floating-point instructions
Advanced SIMD byte permute instructions
Advanced SIMD load/store instructions
Advanced SIMD register transfer instructions
VFP instructions
VFP instruction execution in the VFP coprocessor
VFP instruction execution in the NFP pipeline
Scheduling example
AC Characteristics
About setup and hold times
AXI interface
ATB and CTI interfaces
APB interface and miscellaneous debug signals
L1 and L2 MBIST interfaces
L2 preload interface
DFT interface
Miscellaneous signals
Signal Descriptions
AXI interface
ATB interface
MBIST and DFT interface
MBIST interface
DFT pins and additional MBIST pin requirements during MBIST testing
Preload engine interface
APB interface
Miscellaneous signals
Miscellaneous debug signals
Miscellaneous ETM and CTI signals
Instruction Mnemonics
Advanced SIMD data-processing instructions
VFP data-processing instructions
Glossary
Revision: r2p1
Cortex-A8 Technical Reference Manual
Preface
About this manual
Product revision status
Intended audience
Using this manual
Conventions
Typographical
Timing diagrams
Signals
Numbering
Further reading
ARM publications
Other publications
Feedback
Feedback on the product
Feedback on this manual
Introduction
About the processor
ARMv7-A architecture
Components of the processor
Instruction fetch
Instruction decode
Instruction execute
Load/store
L2 cache
NEON
ETM
External interfaces of the processor
AMBA AXI interface
AMBA APB interface
AMBA ATB interface
DFT interface
Debug
Power management
Configurable options
Product revisions
Programmer’s Model
About the programmer’s model
Thumb-2 instruction set
ThumbEE instruction set
Instructions
Configuration
ThumbEE Configuration Register
ThumbEE HandlerBase Register
Access to ThumbEE registers
Jazelle Extension
Jazelle Identity Register
Jazelle Main Configuration Register
Jazelle OS Control Register
Security Extensions architecture
Security Extensions model
Advanced SIMD architecture
VFPv3 architecture
Processor operating states
Switching state
Interworking ARM and Thumb state
Data types
Memory formats
Byte-invariant big-endian format
Little-endian format
Addresses in a processor system
Operating modes
Registers
The state register set
The program status registers
The condition code flags
The Q flag
The IT execution state bits
The J bit
The GE[3:0] bits
The E bit
The A bit
The control bits
Interrupt disable bits
T bit
Mode bits
Modification of PSR bits by MSR instructions
Reserved bits
Exceptions
Exception entry and exit summary
Leaving an exception
Reset