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ARM Technical Support Knowledge Articles
AMBA
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PL301 AMBA 3 HP Matrix
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All Articles
How do I configure RVD/RVI to capture ETM Trace using RVT on the PB-A8?
"CLOSE-ALL" CRASHES UVISION
"Invalid ROM Table" on STM32 Device
"JVM terminated" error when launching DS-5 / OutOfMemoryError reported when using DS-5
"No MSI installer found" error when installing
"run_example" script fails to link "libmgmm.so" to 64-bit Verilog simulator
#DEFINE FOR #PRAGMA
#DEFINE GENERATES WRONG RESULTS
#DEFINES WITH ARITHMETIC DON'T WORK
#IFDEF CAUSING STRING TEST PROBLEMS
#PRAGMA MESSAGE AND #PRAGMA ERROR
'N' DOES NOT WORK IN PRINTF() STATEMENTS
'REORDER' MAY GENERATE WRONG CODE IN VERSION 5.00
'Unable to set breakpoints on exception vectors' with ROM at address 0
* Does HWDATA have to remain stable during an extended transfer? *
10-PIN / 20-PIN 1.27MM ARM CORTEX DEBUG CONNECTOR
16-BIT MULTIPLY WITH 32-BIT RESULT
16MB XDATA RAM WITH ANALOG DEVICES MICROCONVERTER
256 GLOBAL SYMBOLS LIMIT
4K-LIMITED COMPILER FOR THE PHILIPS LPC FAMILY
51MX LIBRARY PROBLEMS WITH C51 V6.22
64-BIT CALCULATIONS
64-BIT FLOATING-POINT OPERATIONS
64-BIT LONG LONG ARITHMETIC SUPPORT
8051 CLOCK SPEED VS XTAL SPEED
8051 DEVICE SIMULATION SUPPORT
8051 PORT FOR JEAN LABROSSE'S MICRO C/OS-II RTOS
8051 SERIAL I/O IN C
80C517A MA-STEP SHIFT BUG
80C751.LIB IS MISSING FROM EVALUATION CD-ROM
80C751.LIB MISSING FROM RELEASE TOOLS
89LPC932 CHIP REVISIONS
8K LIMIT ON MEMORY ALLOCATION
?C? LIBRARY ROUTINES
?C? LOAD AND STORE LIBRARY ROUTINES
?C? LONG/FLOAT MATH LIBRARY ROUTINES
?C?COPYXX UNRESOLVED EXTERNAL FROM EVAL VERSION
?C_INITSEC AND ?C_CLRMEMSEC FUNCTIONS
?C_INITSEC and ?C_CLRMEMSEC located at wrong address
A/D EXAMPLES FOR THE ADUC812
ABSOLUTE ACCESS FOR FAR VARIABLES
ABSOLUTE ADDRESSES
ABSOLUTE CODE REQUIRES LINKER FOR SYMBOL RESOLUTION
ABSOLUTE CODE SEGMENTS BEYOND 64 KBYTE
ABSOLUTE FAR VARIABLES DO NOT CALL IBANKING FUNCTIONS
ABSOLUTE FUNCTION ADDRESS
ABSOLUTE FUNCTION ADDRESS
ABSOLUTE MEMORY ACCESSES TO DALLAS 390'S FAR MEMORY
ABSOLUTE REGISTERS AND USING DIRECTIVE
ABSOLUTELY LOCATING STARTUP CODE
ACCESS BREAKPOINTS ON ABSOLUTE MEMORY WRIT
ACCESS BREAKPOINTS ON CYGNAL HARDWARE
ACCESS LOW/HIGH BYTES OF A INTEGER VARIABLE
ACCESS PROBLEM WITH XC16X ON-CHIP FLASH
ACCESS RTC IN ST10-F269
ACCESS TO PAGED SFR REGISTERS
ACCESS VIOLATION 0X00C000 WITH XC16X
ACCESSING A POINTER IN ASSEMBLER
ACCESSING A STRUCTURE VIA A POINTER
ACCESSING ASSEMBLY ECODE VARIABLES FROM C
ACCESSING ASSEMBLY VARIABLES FROM C
ACCESSING BITS ON P5 OF PHILIPS 552
ACCESSING EXTENDED CODE SPACE THE DS80C400
ACCESSING EXTERNAL SFR'S IN A C PROGRAM
ACCESSING GLOBAL VARIABLES DEFINED IN C CODE
ACCESSING I/O PORTS IN C
ACCESSING INTERNAL EEPROM ON ATMEL 89S9252
ACCESSING MANY PORT BITS WITH THE SAME CODE
ACCESSING PDATA VARIABLES IN ASSEMBLER
ACCESSING REGISTER BANKS IN C
ACCESSING SPECIAL FUNCTION REGISTERS IN C
ACCESSING SPECIAL VARIABLE NAMES
ACCESSING SPECIFIC BYTES OF AN EXPRESSION
ACCESSING SPECIFIC MEMORY BYTES
ACCESSING THE DS390 ON-CHIP 4K SRAM AND STACK
ACCESSING THE FULL ADDRESS RANGE
ACCESSING THE FULL MEMORY SPACE
ACCESSING THE USER STACK VIA DPP2
ACCESSING XDATA MEMORY AT NON-STANDARD ADDRESSES
ACQUIRE/RELEASE OR BINARY SEMAPHORE IN RTX KERNEL
ACQUIRING CARM COMPILER FOR CURRENT REALVIEW MDK VERSION
ACTEL A2F SMARTFUSION TARGET BOARDS
ACTEL CORTEX-M1 ENABLED PROASIC3 DEVELOPMENT KIT SUPPORT
ACTIVATION REQUIRED ON ALL WORKSTATIONS?
ADC DOES NOT DELIVER PROPER VALUES
ADD LIC BUTTON IS NOT ACTIVE
ADD WIGGLER SUPPORT TO C166 VERSION 6
ADD-ON COMPONENTS FOR CD 06.2006
ADDING A LIBRARY TO A PROJECT
ADDING A USER-SPECIFIC DEVICE DATABASE (CDB FILE)
ADDING C FUNCTIONS TO EXISTING ASSEMBLER CODE
ADDING CUSTOM PARTS TO THE DEVICE DATABASE
ADDING HEADER FILES TO A PROJECT
ADDING INTRINSIC FUNCTIONS
ADDING KEYWORDS TO UVISION
ADDING LIBRARY FILES TO A PROJECT
ADDING OR CHANGING RECOGNIZED KEYWORDS
ADDING SEMAPHORE SUPPORT
ADDING THIRD PARTY DLL SUPPORT IN TOOLS.INI
ADDING TO THE STARTUP CODE
ADDRESS PADS ARE REVERSED
ADDRESS SPACE OVERFLOW WITH FAR CONST
ADDRESSING BITS AND BYTES
ADS 1.0.1 AXD reports "DBE Warning 00041: An unspecified Debug Toolbox call failed"
ADS 1.1 ARMulator peripherals at addresses > 0x80000000
ADS 1.1 AXD: 'axd.vbs' could not be opened
ADS 1.1 AXD: Session file could not be loaded
ADS 1.1 Compiler reports "Fatal error: Internal fault: 0xca5f"
ADS 1.1 armasm: Error: A1140E: Bad operand type
ADS 1.1: Scatterloading of mixed ARM and Thumb projects with CodeWarrior
ADS 1.2: CodeWarrior hangs when opening a Target Settings window
ADUC7020 MAPS ADCBUSY TO JTAG TRST SIGNAL
ADUC812 COMPATIBILITY
ADUC812 COMPATIBILITY
ADUC812 EXAMPLE PROGRAM
ADW reports "This version of the ARM debugger cannot use this driver"
AFTER REGLIVE SUCCESS MESSAGE
AGDI SPECIFICATION
AHB Protocol: Must a read after a write to the same address return the newly written data?
AHB-lite - Can HWDATA change in the 2nd cycle of an ERROR response ?
ALIGNMENT FOR CHAR AND SHORT
ALIGNMENT PROBLEM WITH VARIABLES WITH GNU
ALTERNATE STARTUP CODE
AMAKE BUILDS FOREVER
AMBA Designer requirements for installing PL301r1p2
ANALOG COMPARATOR ON AT89C2051
ANALOG DEVICES ADUC812 EXTERNAL CODE PROBLEMS
APPLICATION ERROR WHEN CONVERTING LEGACY CODE
APPLICATION MANAGER STRING SUBSTITUTIONS
APPLICATION ONLY WORKS WITH EPM900
AR166 HANGS IN OS_SYS_INIT
ARCHIMEDES COMPILER SUPPORT
ARCHIVE TOOL VERSIONS
ARE 32-BIT SFRS SUPPORTED?
ARE ANONYMOUS STRUCTURES SUPPORTED?
ARE ARM7 32/64-BIT MAC INSTRUCTIONS SUPPORTED?
ARE CHECKSUM LIBRARY ROUTINES INCLUDED?
ARE CODE AND DATA OBJECTS RELOCATABLE?
ARE I/O PINS 5V TOLERANT?
ARE LINK AND MAKE FUNCTIONS AVAILABLE?
ARE MANUALS AVAILABLE?
ARE RAM BIT-ADDRESSABLE REGISTERS SUPPORTED?
ARE THE KEIL TOOLS Y2K COMPLIANT?
ARE UNIONS SUPPORTED IN C51
ARE WIDE CHARACTER (UNICODE) STRINGS SUPPORTED
AREGS/NOAREGS DIRECTIVE
ARGUMENT INVALID WHEN USING DEBUGGER FUNCT
ARITHMETIC PROBLEMS WITH CHAR TYPES
ARM Compiler and 64-bit filesystems
ARM Compiler optimizations
ARM Compiler toolchain and DS-5 terminology and versioning
ARM DEBUGGER CRASHES
ARM PERIPHERALS SIMULATION PROBLEMS
ARM SUPPORTS ONLY TWO BREAKS IN FLASH ROM
ARM website Product pages recommend CMSDK bit banding, but CMSDK TRM does not
ARM946E-S use of HLOCK / Problems with the ARM946E-S in my AHB system when a SWP is executed
ARM:SIMULATING LPC2478 LCD CONTROLLER
ARMulator benchmarking with RVD
ARRAY INDEX ARITHMETIC
ARRAY INDEX USES BYTE INSTEAD OF WORD
ASCII CHART
ASM/ENDASM DIRECTIVE
ASM/ENDASM DIRECTIVE
ASMEXPAND DIRECTIVE
ASMEXPAND/NOASMEXPAND DIRECTIVE
ASSEMBLER DOES NOT EXCLUDE FORMFEEDS
ASSEMBLER PROBLEMS IMPORTING C251 SOURCE-MODE
ASSEMBLY CODE FOR CRC-16 FOR SDLC
ASSIGNED COM PORTS USE XON/XOFF
ASSIGNING AN I/O ADDRESS TO A VARIABLE
ASSIGNING BINARY VALUES TO VARIABLES
ATMEL AT91SAM7 DEVICE DOES NOT REACT
ATMEL DEVICE SUPPORT
ATMEL DEVICES WITH EXTERNAL UART DO NOT WORK
ATMEL EEPROM PROGRAMMING SUPPORT
ATMEL FLASH PROGRAM UTILITY FLIP
ATMEL FLIP AS DOWNLOAD UTILITY
ATMEL REMAP CAUSES PROBLEMS WITH
ATMEL SAM-ICE SUPPORT
ATMEL T89C51CC01 INTERNAL EEPROM SUPPORT
ATOF LIBRARY ROUTINE USES BIT VARIABLES
ATOMIC EXECUTION SEQUENCES
AUTOMATED SERIAL INPUT SCRIPT
AUTOMATED TEST NEVER STOPS
AUTOMATIC GENERATION OF LOOKUP TABLES
AUTOMATICALLY LOADING AN INCLUDE FILE
AUTOMATICALLY RENAMING OBJECT FILES
AVOIDING ACALL PROBLEMS IN DS80C390 REV BX DEVICES
AVOIDING CODE IN INTERRUPT VECTOR SPACE
AVOIDING FUNCTION POINTER PROBLEMS WITH NOOVERLAY
AVOIDING MOVC FETCHES FROM CODE SPACE
AVOIDING STARTUP INITIALIZATION OF STATIC VARIABLES
AVOIDING THE USE OF REGISTER BANK 0
AVOIDING WARNING 7 (MODULE NAME NOT UNIQUE)
AXD reports "RDI Warning 00148: Can't set point"
Accessing 64-bit peripherals using Cortex-M processors
Accessing Cortex-A9MP's global timer causes abort
According to the TRM, nMREQ is only deasserted (to '1') preceding an Internal or coprocessor cycle. Why is it deasserted during an LDR instruction?
Adding ADS 1.2.1 (RVDS) licenses to an existing ADS license server
Adding source files to an existing project
After executing a BX instruction to change into Thumb state, the ARM7TDMI is outputting addresses with A[0] set. Why is this?
After starting with nohup, how can I find the Java processes related to each component in Linux?
All Eclipse views disappear when RSE is updated
Arbitration: Can a master deassert HLOCK during a burst?
Arbitration: Can a master perform transfers other than IDLE when the bus was granted to it, but not requested by the master?
Arbitration: If a master is currently granted the bus by default, how many cycles before starting an non-IDLE transfer does it have to assert HBUSREQ?
Arbitration: What is the relationship between the HLOCK signal and the HMASTLOCK signal?
Arbitration: When can the HGRANT signal change?
Arbitration: Why is HADDR sometimes shown as an input to the arbiter?
Are RTL descriptions of ARM cores available to universities and research organizations?
Are TLBs in same power domain as ARM core logic ?
Are device drivers available for the PL330?
Are legacy objects and libraries compatible with my project?
Are nFIQOUT/nIRQOUT active during L2 STANDBYWFI state ?
Are the Cortex-M3's INTISR signals synchronous or asynchronous?
Are the IRQ and FIQ interrupts level-sensitive?
Are the PL011 UART and APB clocks synchronous?
Are the Virtex-II and Virtex-4 Logic Tiles compatible?
Are there ARM forums that exist to answer my technical questions?
Are there ARM720T core test vectors in JTAG serial test format?
Are there any design changes in lead free boards?
Are there any issues related to hazard detection on overlapping locations?
Are there any issues with exclusive accesses passing from one width of data bus to another?
Are there any known problems with the BERROR signal? (Rev 0-3)
Are there any recommendations about the types of accesses that are used for atomic accesses?
Are there any recommendations for verifying AXI components?
Are there any special requirements for using an SMP target with Streamline?
Are there are any special considerations when memory mapping hardware registers?
Are there free software development tools available?
Are there special TCK considerations (like adaptive clocking) when the core is used within an AHB wrapper?
Are there updates to older versions of TRMs or TRM Errata Lists?
At what frequency can TRACECLKIN be run?
At what point can the master consider that the transaction has been accepted by the slave such that the responsibility for hazard checking lies with the slave?
At what point in an AXI bus transfer is davalid asserted?
Avoiding spurious ECC errors in Cortex-M7 TCM
BAD JUMP IN .SRC FILE
BANK SWITCH MODE 1 CAUSES SPORADIC RUN-TIME ERRORS
BANK SWITCHING COMMON AREA
BANK SWITCHING USING ASSEMBLY
BANK TABLE ENTRIES FOR INDIRECTLY CALLED FUNCTIONS
BANKSWITCHING IS NOT AVAILABLE IN V2
BATCH FILE FOR BANKED APPLICATIONS
BATTERY-BACKED NON-VOLATILE MEMORY
BAUD RATES
BIT ADDRESSABLE ARRAYS
BIT FIELD UNIONS DON'T WORK AS EXPECTED
BIT FIELD UNIONS GIVE STRANGE RESULTS
BIT FORMAT SPECIFIERS FOR PRINTF
BIT-ADDRESSABLE DATA VARIABLES
BITS USED FOR BANK SELECTION
BLANK COLUMN IN TEXT EDITOR
BLANK ROM ON EVAL BOARD
BOOTING FROM FLASH BANK1
BOOTLOADER AND ISP FOR THE CYGNAL C8051FXX DEVICES
BOOTLOADER EXAMPLES
BOOTLOADING THE PHYTEC LPC3180
BREAKPOINT PROBLEMS WITH INFINEON XC800 DEVICES
BREAKPOINTS IN MEMORY REGIONS
BREAKPOINTS LOST WITH SEVERAL APPLICATIONS
BROWSE DIRECTIVE
BROWSER INFORMATION IN OMF51 FILE MAKES EMULATOR FAIL
BST Language not supported well in Serial Wire mode
BUILD OPTION REBUILDS ALL TARGET FILES
BUILD TARGET ALWAYS RECOMPILES ALL FILES
BUILD TARGET REBUILDS ALL FILES WHEN TZ IS SET
BUILD TARGET RETRANSLATES NOAMAKE FILES
BUILDING PROGRAMS FROM MS VISUAL STUDIO
BUILDING TARGETS FROM THE COMMAND LINE
BURNING EPROM FROM BL51 FILES
BYTE-WISE ACCESS TO FLOAT VALUES
BYTEALIGN DIRECTIVE
BYTES IN RAM APPEAR TWICE
Benefits of PL310 r3p0 Data RAM banking
Bit-Addressable Registers in Assembly Code
Bit-banded accesses versus read-modify-write accesses
Booting a Cortex-M7 system
Breakpoints on inline C/C++ functions
BuildCORTEXM7_DSM.pl script gives "cannot stat `<path>/execution_tb/tests/*.<ext>': No such file or directory" messages for cp: and mv:
Building a C++ project without floating-point libraries
Building applications using GCC on an Ubuntu host fails
C FILE ALWAYS RECOMPILED WHEN CREATING SRC FILES
C MACRO EXPANSION PROBLEM WITH PARAMETERS
C STANDARDS
C library character and string function problems
C153 WARNING APPEARS USING C166 V4.24
C166 UTAH SUPPORT
C167CR CAN SUPPORT
C16X OCDS DEBUGGING VIA LPT INTERFACE
C8051F330 OSC READY BIT NOT SET IN SIMULATOR
C9X SPECIFICATIONS
CALCULATING BAUD RATES FOR THE 8051 SERIAL PORT
CALCULATING CODE SPACE FOR BANK SWITCHING
CALCULATING STACK SIZE
CALCULATING TIMER SETTINGS FOR SERIAL I/O
CALDP.LIB NOT FOUND
CALL C FUNCTIONS WITHIN STARTUP CODE
CALL GIVES WARNING L21 (DATA TYPES SLIGHTLY DIFFERENT)
CALL TREE USING POINTERS TO FUNCTIONS
CALLING ASSEMBLY ROUTINES FROM C
CALLING BOOT LOADER FUNCTIONS FROM USER APPLICATION
CALLING C FUNCTIONS FROM ASSEMBLY
CALLING FUNCTIONS FROM INTERRUPTS
CALLING OS_DISABLE_ISR INSIDE AN INTERRUPT
CALLING PRINTF FROM AN INTERRUPT
CALLING PRINTF FROM MULTIPLE TASKS
CALLING PRINTF IN AN INTERRUPT
CAN 29-BIT PROBLEMS
CAN BUS DOES NOT WORK UNDER MONITOR TESTING
CAN COMMUNICATION QUESTION
CAN CONTROLLER FAILS WITH C167CR CPU FA/GA STEP
CAN I COMPILE WITH AN EXPIRED LICENSE?
CAN I EXECUTE ARM CODE FROM RAM?
CAN I MOVE THE .FLF FILE?
CAN I USE A FLOATING LICENSE OFF-LINE?
CAN INTERFACE PROBLEMS
CAN INTERFACE PROBLEMS
CAN MESSAGE 15 MASKING
CAN SIMULATION PROBLEMS WITH THE C167C
CAN STRUCT MEMBERS RESIDE IN DIFFERENT MEMORY SPACES?
CAN SUPPORT FOR C505C AND C515C
CAN THE TOOLS TRANSLATE ASSEMBLY TO C?
CAN'T ASSEMBLE SRC FILES
CAN'T BREAK AT ISR USING OCDS AND XC16X
CAN'T DEBUG CHIPCON DEVICES
CAN'T DEBUG WITH USB TO RS232 ADAPTER
CAN'T DEFINE TASKS IN EC++
CAN'T DISPLAY DPROBE.PDF FILE
CAN'T EXECUTE "C:KEILUV2KSPAWN.EXE" ERROR
CAN'T EXECUTE ARM ASSEMBLER
CAN'T EXECUTE C51.EXE, C251.EXE, OR C166.EXE
CAN'T EXECUTE CX51.EXE
CAN'T FIND IN V6 INSTALLATION
CAN'T FIND MON251.DLL
CAN'T FIND SIC8051F.DLL AFTER INSTALLING UPGRADE
CAN'T LOCATE DEVICE BOOKS USING DEFAULT ROOT
CAN'T OPEN BOOKS PDF FILE
CAN'T OPEN PDF MANUALS
CAN'T SINGLE-STEP THROUGH TARGET CODE ABOVE 0X400000
CAN'T WATCH A, B, AND C VARIABLES IN DEBUGGER
CANNOT ACCESS MEMORY ON TI LM3S9B96 DEVICE
CANNOT BREAKPOINT UPSD DEVICES
CANNOT COMMUNICATE VIA THE CAN PORTS
CANNOT CONNECT TO DALLAS TINI 400'S SERIAL PORT 0
CANNOT DEBUG LPC2378 OR LPC2368 DEVICE
CANNOT DEBUG ON LUMINARY LM3S811-EV BOARD
CANNOT FIND ?C?COPYP2 LIBRARY FUNCTION
CANNOT FIND DEMO USB DRIVERS
CANNOT LOAD FLASH PROGRAMMING ALGORITHM
CANNOT LOCATE SEGMENTS
CANNOT LOCATE TOOLS
CANNOT PROGRAM UPSD3422 DEVICE
CANNOT READ *.SBR FILE WHEN USING SOURCE BROWSER
CANNOT RENAME THE DEVICES IN JTAG CHAIN
CANNOT SAVE SOURCE FILES
CANNOT SINGLE-STEP IN BOOSTRAP MODE
CANNOT TYPE CHARACTERS INTO SERIAL WINDOW
CANOPEN AND DEVICENET SUPPORT
CANREGS.H
CAPACITOR VALUE ON BOARD
CARRYING A #DEFINE MACRO OVER TO THE NEXT LINE
CASTING A VARIABLE ON THE STACK TO A CODE POINTER
CE APPROVAL
CE APPROVAL
CE APPROVAL
CE APPROVAL
CE APPROVAL
CHAINING JTAG DEVICES
CHANGE CAN INTERFACE ON XC16X DEVICES
CHANGE MESSAGE SIZE OF USBHID EXAMPLE
CHANGING BASE OF VARIABLES IN WATCH WINDOW
CHANGING EDITOR FONT TYPE, SIZE, COLOR
CHANGING FILE PATHS IN A PROJECT AFTER IMPORTING
CHANGING L51_BANK TO OUTPUT INVERTED SIGNALS
CHANGING OPTIMIZER LEVEL FOR A SINGLE FUNCTION
CHANGING ORDER OF FILES/GROUPS IN A PROJECT
CHANGING PRINTER SETTINGS
CHANGING RESET VECTOR ADDRESS
CHANGING STACKS FOR CUSTOM RTOS
CHANGING SYNTAX COLORING
CHANGING THE LOCATION OF THE RESET VECTOR
CHANGING THE ORDER OF OBJ FILES MAKES PROGRAM CRASH
CHANGING THE PROGRAM COUNTER
CHANGING THE SYSTEM STACK SIZE AND LOCATION
CHECK USAGE OF SPECIFIC COMPILER VERSIONS
CHECKING FOR CORTEX-M3 LDRD ERRATA 602117
CHECKING FOR STACK UNDERFLOW AT RUNTIME
CHECKING TOOL FOR XC800 CHIP BUG
CHM FILES STOP WORKING IN WINDOWS XP
CLEAR EXIT CODE OF EXTERNAL USER PROGRAMS
CLEARING THE SCANF INPUT STREAM
CLOCK TICKS AND TIME SLICE
CLOSES WITHOUT SAVING CHANGES
CM1136JF-S has 16KB caches and TCMs
COD LISTINGS FOR ASSEMBLY FILES
CODE ADDRESS SPACE OVERFLOW WITH ROM(HUGE)
CODE BANKING GENERATES ERROR L124
CODE BANKING LATCH ON EXTRA ADDRESS LINES
CODE BANKING SUPPORT
CODE BANKING WITH C51 V6
CODE BANKING WITH ON-CHIP AND OFF-CHIP MEMORY
CODE BANKING WITH SILABS C8051F12X/F13X DEVICES
CODE DIRECTIVE
CODE DIRECTIVE
CODE GENERATOR SUPPORT FOR MULTIPLE DATA POINTERS
CODE LOAD VERY SLOW
CODE PACKING PROBLEM WITH C51 V7.50
CODE STRINGS IN STRUCTS ARE NOT MERGED
CODE VS ECODE
COLOR SYNTAX HIGHLIGHTING SUPPORT FOR PL/M
COLUMN INDICATOR COUNTS TABS AS SPACES
COM1 (UART0) DOES NOT WORK
COMBINING CODE BANKING HEX FILES
COMMAND LINE GLOBAL REGISTER OPTIMIZATION
COMMENTING OUT MACRO DEFINITIONS
COMMENTS IN ASSEMBLY BLOCKS
COMMENTS IN MACROS
COMMON DO-178B CERTIFICATION QUESTIONS
COMMONRET DIRECTIVE
COMMUNICATING WITH TARGET AFTER GO COMMAND
COMMUNICATION BETWEEN BOOTLOADER AND APPLICATION
COMMUNICATION STOPS WITH THE EZ-USB BOARD
COMPACT DIRECTIVE
COMPATIBILITY WITH C51 V5.1 AND C51 V5.5
COMPATIBILITY WITH CYGNAL SFR PAGING
COMPILER APPEARS TO PLACE VARIABLES IN SFR MEMORY
COMPILER DIRECTIVE FOR LINKER-LEVEL OPTIMIZATION
COMPILER DIRECTIVE FOR OMF-51 EXTENDED FORMAT
COMPILER DIRECTIVE FOR OMF2 FILE FORMAT
COMPILER DOES NOT INITIALIZE R1/R2/R3 FOR ?C?CSTOPTR
COMPILER DOESN'T WORK WITH BORLAND MAKE
COMPILER GENERATES ZERO LENGTH JUMP
COMPILER IGNORES 0XFD, 0XFE, 0XFF VALUES IN STRINGS
COMPILER INITIALIZES GLOBAL VARIABLES TO 0
COMPILER IS UNABLE TO FIND INCLUDE FILES
COMPILER OPTIMIZES OUT NECESSARY XDATA READS
COMPILER OR ASSEMBLER ERRORS
COMPILER RUNS SLOWLY UNDER NT
COMPILER USES DPL AND DPH FOR VARIABLES
COMPILES FOREVER
COMPUTER SCREEN BLANKS WHEN BUILDING A PROJECT
COND/NOCOND DIRECTIVE
COND/NOCOND DIRECTIVE
CONDITIONAL ASSEMBLY CODE
CONDITIONAL BREAKPOINTS WITH STM32 DEVICES
CONFIGURABLE SFR BIT ACCESSES
CONFIGURATION FAILS WITH C166 V5.04
CONFIGURATION FILES
CONFIGURATION FILES FOR VERSION CONTROL SYSTEMS
CONFIGURATION FOR A VON NEUMAN ARCHTECTURE
CONFIGURATION FOR CYGNAL DEVICES
CONFIGURE DONGLE DRIVER FOR TOSHIBA NOTEBOOK
CONFIGURE FOR SILABS C8051F12X OR C8051F04X
CONFIGURING FOR 2-BYTE INTERRUPTS
CONFIGURING FOR AT89C51SND1 DEVELOPMENT KIT
CONFIGURING FOR DALLAS DS5000
CONFIGURING FOR MORE THAN 64K OF RAM
CONFIGURING FOR TARGET
CONFIGURING FOR THE DALLAS 390 CONTIGUOUS MODE
CONFIGURING FOR THE EXTERNAL CLOCK
CONFIGURING MALLOC FUNCTION
CONFIGURING PC-LINT
CONFIGURING PPAGE AND PPAGEENABLE
CONFIGURING THE HTTP_DEMO PROGRAM
CONFIGURING THE USB SECURITY KEY DRIVER
CONFIGURING XDATA BANKING
CONFIGURING XDATA LATCH FOR CODE BANKING
CONFLICT BETWEEN DATA AND CODE MEMORY
CONFLICTING FUNCTION TYPE AND RETURN TYPE
CONNECTING TO A TERMINAL DOESN'T WORK
CONNECTING ULINK2 TO TI/LUMINARY BOARD
CONNECTION ISSUES WITH INFINEON XE16X/XC2XXX DEVICES
CONNECTION ISSUES WITH ULINK AND XC161 AC STEP
CONNECTION TO TARGET SYSTEM LOST
CONST ARRAY IN ROM
CONST VARIABLE BANKING WITH SILABS C8051F12X DEVICES
CONST VARIABLE STORAGE LOCATION
CONSTANT ARRAYS LARGER THAN 64KB
CONSTANT FLOATING POINT NUMBER '0E'
CONSTANT VALUES AT FIXED ADDRESSES IN CODE SPACE
CONSTANTS IN SPECIFIC MEMORY AREAS
CONTENTS OF THE ?C_INITSEG SEGMENT
CONTROL DIRECTIVES
CONVERSION PROCESS FOR DEBUG SYMBOLS FOR EMULATORS
CONVERTING A PROJECT TO MICROLIB
CONVERTING BIG ENDIAN TO LITTLE ENDIAN
CONVERTING C167 PROGRAMS TO THE C161
CONVERTING FLOATING-POINT NUMBER TO INTEGER
CONVERTING IAR BANKED CODE TO KEIL
CONVERTING LEGACY 8051 ASSEMBLY CODE TO KEIL C51/A51
CONVERTING MACRO PARAMETERS TO STRINGS
CONVERTING PORT.BIT CODE FROM IAR
CONVERTING PROGRAMS FROM GNU
COPYING C INTERRUPT ROUTINES TO IDATA IN V3.X
COPYING CD-ROM DATASHEETS TO YOUR HARD DRIVE
COPYING FUNCTIONS TO RAM FOR EXECUTION
CORRECTED SETJMP.H FOR CX51
CORRECTLY DECLARING VARIABLES WITH MEMORY SPACES
CORRUPTION OF DPTR WHEN USING MODP2
CORTEX M3 HANGS WITH A HARD FAULT
CORTEX MICROCONTROLLER SOFTWARE INTERFACE STANDARD
CORTEX-M3 DEVICE SIMULATION RESULT DIFFERS FROM REAL HARDWARE
CORTEX-M3: DETECTING DEBUG CONTROL
COULD NOT EXECUTE TRANSLATOR
COULD NOT EXECUTE TRANSLATOR
COULD NOT FIND COMMAND FILE (LINKER ERROR)
COUNTING SET BITS IN A BYTE
CPU STARTS AT ADDRESS 0X410000
CPU.21 ERRATA PROBLEMS AND FIXBFLD DIRECTIVE
CPU.22 ERRATA PROBLEM: Z FLAG AFTER PUSH AND PCALL
CRASH ON RIGHT-CLICK IN PROJECT WINDOW
CRASHES AFTER CALLING OS_START_SYSTEM
CRASHES AFTER MONITOR IS REBUILT
CREATE A PATCH VECTOR TABLE
CREATE HEX FILES FOR CODE BANKING APPLICATIONS
CREATE LIBRARY AND APPLICATION IN ONE PROJECT
CREATING A FIXED STACK SEGMENT
CREATING A HEX FILE WITH CONSTANTS ONLY
CREATING A LIBRARY
CREATING A PROJECT BATCH FILE
CREATING C FILES FROM BINARY OR HEX DATA
CREATING CODE BANKING PROGRAMS
CREATING CPU HEADER FILES
CREATING DATA-ONLY HEX FILES
CREATING FLOATING-POINT CONSTANTS
CREATING HEX FILES FOR THE CYPRESS USB DEVICES
CREATING INI FILES
CREATING INPUT SIGNAL PATTERNS
CREATING INTEL HEX FILES
CREATING INTERRUPT VECTOR TABLES IN ASSEMBLY
CREATING LIBRARY FILES
CREATING MOTOROLA S-RECORD FILES
CREATING MULTI PROJECT WORKSPACES
CREATING OUTPUT FILES FOR OLDER PHILIPS PDS51 EMULATORS
CREATING TARGETS FOR FLASH AND MONITOR
CREATING TEMPLATES FOR VERSION CONTROL SYSTEMS
CS8900.H HEADER FILE IS MISSING
CUSTOM SIMULATION DLLS
CUSTOM TRANSLATOR
CUSTOMIZING MON51
CUSTOMIZING THE STARTUP CODE
CYGNAL DLL DEVICE SELECTION PROBLEMS
CYGNAL DOWNLOAD VIA DLL AFFECTS CHECKSUM
CYPRESS EZ-USB EVALUATION BOARD COMMUNICAT
CYPRESS EZ-USB FX MONITOR CONNECTION
CYPRESS EZ-USB MONITOR PROGRAMS
Can AArch32 and AArch64 objects be linked together?
Can ARM provide sample source code to uncompress compressed textures?
Can ARM11 enter standby mode during debug ?
Can AXI masters connected to CCI-400 through a NIC-301 snoop the ACE master caches?
Can AXI-based ARM cores generate bursts across 1KB boundaries?
Can BVALID be asserted before WLAST in a write transaction?
Can Cortex-M3 / Cortex-M4 make a simultaneous instruction fetch and data access to Code space?
Can Cortex-M3 measure the cycle count of its own activity?
Can Cortex-M3/4 have a pending Halt after Reset?
Can Cortex-M4 interrupt the Lazy Stacking operation?
Can DMA-330 perform Scatter-gather to unaligned addresses?
Can DMA-330 support >32-bit addresses?
Can DS-5 debug Android?
Can I access RAM on the CoreTile Express A9x4 from my custom IP on the LogicTile Express?
Can I access the DTCM via DMA even if the core is in standby mode?
Can I benchmark a core using an ISSM?
Can I benchmark an ARM11 with RVISS/ARMulator?
Can I benchmark my code using an RTSM?
Can I boot Linux in the Normal world on the Cortex-A8 EB RTSM?
Can I boot my core using the PL022 Synchronous Serial Interface?
Can I boot the Linux kernel on the RTSMs provided with RVDS?
Can I change a three server license into a single server license?
Can I change the value of msync and async after the power supply is turned on?
Can I choose which counter my PL330 program uses?
Can I connect Model Debugger / DS-5 Debugger to the Foundation model?
Can I connect Multi-ICE to the core as it exits reset? What is “Reset system on startup�
Can I connect a CCI-400 ACE-Lite master interface to an AXI3 slave interface on a NIC-301?
Can I connect my own DDR PHY with ARM PL34X DDR Memory controllers or is it restricted only to ARM Artisan DDR PHY?
Can I connect the ETB's AHB interface in a big-endian memory system?
Can I connect to RVI over USB?
Can I connect to an ARM core with a debugger if it is daisy-chained with non-ARM devices?
Can I convert CodeWarrior projects into RVD projects?
Can I debug Linux Applications and Kernel modules using RVD?
Can I debug my Linux kernel with RVD?
Can I debug relocated code at source-level with DS-5 Debugger?
Can I decrease the time taken by RVDK for OKI to build my application?
Can I define the order in which different version licenses are issued?
Can I download an evaluation version of the RealView Development Tools?
Can I have more than one Visualization in a single system?
Can I have more than one version of the CodeWarrior IDE on my PC?
Can I hook up my ARM1176 to a L2 cache ?
Can I increase the number of processes allowed by the Fast Context Switch Extensions?
Can I individually reset each core in the CoreTile Express A9x4?
Can I individually set refresh periods for each connected memory chip?
Can I install ADS and RVDS on the same machine?
Can I install RVCT for BREW 1.2 and 3.0 on the same PC?
Can I install RVDK for OKI on a PC which has other ARM tools installed?
Can I instantiate multiple EVSs in SystemC?
Can I link ARMv7-M objects with ARMv7-R or ARMv7-A objects and run the resulting image on an ARMv7-R or ARMv7-A processor?
Can I make the ARM compilation tools report all warnings as errors?
Can I monitor/trace PVBus connections?
Can I perform JTAG debug if DBGEN is tied LOW?
Can I place APB system peripherals in the External Private Peripheral Bus (External PPB) space?
Can I preload Tightly Coupled Memories (TCMs)?
Can I preload caches and registers with data?
Can I prevent my interrupt handlers from being interrupted?
Can I profile a Fast Model Virtual Platform with the ARM Profiler?
Can I program the Virtex-4 Logic Tile with ProgcCrds for Multi-ICE?
Can I reprogram CM922T-XA10 Flash without Multi-ICE?
Can I reprogram my board with RealView ICE?
Can I reserve floating licenses for specific users?
Can I run ETM7 validation using ARM7-S
Can I run Linux on the ARMv8-A foundation model?
Can I run the IK test on my netlist?
Can I save the state of a simulation containing a DSM and restart it from the saved state?
Can I set the MPU to prevent any further modification of the MPU settings?
Can I set the memory latencies for a RTSM?
Can I simulate my DSMs under RedHat Enterprise Linux 3.0?
Can I specify which test chip I want on my ARM development board?
Can I stack Logic Tiles?
Can I stack a Logic Tile on (Integrator CP + IM-LT3 + CT)?
Can I upgrade older versions of academic priced ARM development tools and hardware for free?
Can I use "named registers" to access coprocessor registers?
Can I use 16-bit memory for Thumb-2 code?
Can I use ADS1.2 and Multi-ICE 2.2 on a Windows 7 machine?
Can I use CodeWarrior with RVDS?
Can I use JTAG production test vectors for rev1 ARM7TDMI on a rev3 ARM7TDMI?
Can I use Multi-ICE to access the JTAG signals directly? Can I use Multi-ICE to program Flash via JTAG?
Can I use RVDK for OKI on Unix platforms?
Can I use RVDK for OKI to develop for other ARM-based systems?
Can I use RVDK for OKI without being connected to the USB-based JTAG debug interface?
Can I use RVXDK to develop for StrongARM-based systems?
Can I use RVXDK to develop for other ARM-based systems?
Can I use RealView ICE with AXD/ADS?
Can I use RealView Trace on Solaris or Linux?
Can I use TDT 1.1.1 with ADS 1.2?
Can I use Visual Studio as a project management tool with RVCT?
Can I use adaptive clocking with a hard macrocell, for example an ARM7TDMI?
Can I use both SWO Single Wire Output and the Parallel Trace Port for trace?
Can I use code generated by RVDK for OKI with other toolchains?
Can I use existing makefiles with RVD?
Can I use my ARM926 code for an ARM11 core ?
Can I use my DSM on my 64-bit machine?
Can I use my existing RealView Trace unit for hardware profiling using RealView Profiler?
Can I use something other than CLKOUT to clock the RAM blocks?
Can I use the ARM tools with a remote license server?
Can I use the ARM926 with a single-layer AHB system?
Can I use the Eclipse Plug-ins for RealView Development Suite with any version of Eclipse?
Can I use the same name for a load region and an execution region?
Can I use wait-states on the IOP Port of Cortex-M0+?
Can I write to the PL080 registers using AHB bursts?
Can Mali-400 MP support out-of-order transactions?
Can PL111 be run at maximum resolution in 24bpp TFT mode?
Can PL230 generate unaligned accesses?
Can PL340 support 512MByte memory?
Can RVCT 2.0 co-exist with ADS or RVCT 1.2 ?
Can Streamline and Gator daemon send data over an interface other than Ethernet?
Can WLAST or RLAST be high when the relevant xVALID signal is low ?
Can a Cortex-M3/M4 check the contents of the ETM by reading the TPIU Integration Registers?
Can a master change the control signals for different transactions in a locked sequence?
Can a piece of code be locked into the cache?
Can an AHB WRAP burst cross a 1KB boundary?
Can an arbiter be designed to always allow bursts to complete?
Can an exclusive access use sparse write data strobes?
Can an unlocking transaction be an exclusive access?
Can custom logic in a LogicTile Express board directly drive the peripheral interfaces on the V2M-P1 motherboard?
Can give me some information about COMMTX signal and on its active level ?
Can non 64B aligned WRAP4 write transfers occur on Cortex-A7 ?
Can non-secure cache maintenance operations evict secure lines from the data cache?
Can not connect to J-Link via USB.
Can production test vectors be used to determine the maximum core speed of the ARM?
Can register slices be added to PL300?
Can the ADK Interrupt Controller accept asynchronous interrupts?
Can the ARM Compilers make use of v5TE instructions?
Can the ARM compiler generate exclusive loads and stores (SWP, LDREX, STREX)?
Can the ARM compiler workaround Cortex-M3 erratum 602117 ?
Can the ARM7TDMI-S accept asynchronous interrupts?
Can the Cortex-M3 handle 'dynamic' endian switching?
Can the Cortex-R4 perform unaligned instruction fetches on the AXI-M interface?
Can the Cortex-R4F execute code from Strongly Ordered memory?
Can the MMU set a piece of memory space (SDRAM) to read only?
Can the MTB affect processor performance?
Can the PL192 VIC handle edge-triggered interrupts?
Can the UART PL011 be reset without using a clock?
Can the WVALID signal for a write transfer be active before the AWVALID? If so, how does the interconnect know which slave the transfer is for?
Can the compiler be 'forced' to generate STM instructions?
Can the compiler generate LDRD/STRD instructions to access 64-bit peripherals?
Can the java instructions be disabled for ARM7EJ-S?
Can the number of events exceed the number of configured interrupts?
Can we supply the RTL of the ARM cores to our customer or EDA vendors?
Can we use PL351 low power mode using APB control even if AXI interface low-power signals are tied to inactive level (csysreq=1, cclken=0)?
Can we use delay cell instead of pad to reduce the number of Pads in ASIC design?
Can write responses be re-ordered in the same way that read data can be re-ordered?
Can you explain byte selection in ARM1176 big-endian BE-32 system ?
Can you explain the DAP_WRITE_DPACC macro options in coresight DAP macro language ?
Can you explain the generic timer architecture on Cortex-A7 and Cortex-A15 ?
Can you help me to understand the performance enhancement provided by the addition of the 32-bit AXI peripheral port in the ARM11 processors, as compared to the ARM9?
Can you use the TransferSize value when the PL080 is in Peripheral Flow control mode?
Cannot connect to mDS HTTPS REST interface using Wget or cURL
Cannot load RVI DLL in RVD on Solaris or Linux
Changing PL330 AXI transaction IDs
CodeWarrior can overwrite source files with certain file extensions
Codemux returns illegal "not ready" on IDLE request
Coexistence of earlier versions of AXD with AXD v1.3
Command-line installation on Windows
Compatibility between ADS 1.2, ADS 1.1 and ADS 1.0.1
Configuring a Fast Model for a remote CADI connection
Connecting ULINK2/ULINK-ME to NGX Xplorer boards
Connecting the HRESP signals of an AHB master and an AHB-Lite slave?
CoreSight DK11 Integration Manual ARM DII 0092E defines SoC Part Number[3:0] in both Peripheral ID1 and Peripheral ID0 registers
Cortex-A9 MPCore and Cortex-A5 MPCore SMP initialization example
Cortex-A9 MPCore cached Dhrystone examples
Cortex-A9 MPCore cached Dhrystone examples for Versatile Express
Cortex-A9 TrustZone example
Cortex-M Debug Connectors
Cortex-M0 Integration Kit config_check reports "DBG: 0 (Expected 1) - FAIL" when DBG is set
Cortex-M3 example_tbench simulation (run_example) in Mentor Modelsim/Questasim (MTI) produces duplicate lines in tarmac.log
Cortex-M4 Integration Kit Dhrystone test "dhry" gives: Measured time too small to obtain meaningful results Please increase number of runs
Cortex-M4 Integration Kit test fails immediately with ** TEST FAILED ** (Time: 74920) or similar
Could a Cortex-A53 ACP transfer be merged with a transfer from one of the CPUs ?
Could you tell me all AxPROT values that can be generated on ARM1176 ?
Counting transfers with PL080 in Peripheral flow control mode
Current requirement on power-up
DALLAS 390 HANGS ON MATH OPERATIONS
DALLAS 390 MATH ACCELERATOR OPERATIONS
DALLAS 390/400 INTERRUPTS IN ALTERNATE 64K CODE PAGE
DALLAS 390/400/520 STRUCTURE POINTER INCREMENT PROBLEM
DALLAS 390/400/5240 REENTRANT FUNCTION
DALLAS 400 SIMULATION
DALLAS 80C420 OR 89C420 HEADER FILE?
DALLAS DS400 CONTIGUOUS MODE INSTRUCTIONS
DALLAS DS5240 MODULO-ARITHMETIC ACCELERATOR
DALLAS STARTUP CODE GENERATES ERROR A84
DALLAS TINI BOARD SOFTWARE PROBLEMS
DASHES IN FILENAMES
DATA ABORT WHEN USING SWI FUNCTIONS
DATA MEMORY OVERLAP WHEN USING PRECEDE DIRECTIVE
DATA OVERLAYING PROBLEM WITH STRUCT PARAMETERS
DATA OVERLAYING WITH RTOS APPLICATIONS
DATA PASSED TO SPRINTF GETS CORRUPTED
DATA PROTECTION
DATA SENT TO KEIL FOR PRODUCT LICENSING
DATA TYPE QUESTION
DATA/IDATA USAGE
DATA_GROUP AND STACK PROBLEMS
DATE AND TIME OF TARGET ROUTINES
DATE AND TIME PREDEFINED MACROS
DAVE 2.0 NOT WORKING PROPERLY WITH UVISION 2
DAYLIGHT SAVINGS TIME CHANGE ISSUES?
DBT Warning 00056: Debug table format error at offset 0x0 in area .debug_info
DDE INTERFACE
DEBUG DIRECTIVE
DEBUG DIRECTIVE
DEBUG IN OFF-CHIP FLASH OF PHILIPS LPC22XX
DEBUG PROGRAMS IN OFF-CHIP RAM
DEBUG PROGRAMS IN ON-CHIP RAM OF PHILIPS LPC2000
DEBUG WITH ULINK AND OFF-CHIP MEMORY
DEBUGGER HANGS DEBUGGING SMARTFUSION BOARD
DEBUGGER IN C51 V6 VERSUS DSCOPE IN C51 V5
DEBUGGER START DOES NOT RUN TO MAIN
DEBUGGER WON'T HALT RTX51 USING MON51
DEBUGGER WON'T STOP ON BREAKPOINTS, ON ST UPSD33XX
DEBUGGING A51 MPL MACROS
DEBUGGING AN EXISTING HEX FILE
DEBUGGING ASSEMBLER INCLUDE FILES
DEBUGGING CODE RUNNING ON HARDWARE
DEBUGGING INTERRUPTS FAILS FROM INTERNAL FLASH
DEBUGGING LPC2000 APPLICATIONS IN IDLE MODE
DEBUGGING OF AT91C51RB2
DEBUGGING PROGRAMS IN FLASH USING A MONITOR
DEBUGGING RTX51 TINY APPLICATIONS, PART 1
DEBUGGING RTX51 TINY APPLICATIONS, PART 2
DEBUGGING STM32 DEVICES USING ETM
DEBUGGING W/DALLAS DS5250 MONITOR
DEBUGGING WITH ST-LINK THROUGH A USB HUB
DEBUGGING WITH START ADDRESS OTHER THAN 0
DEBUGGING WITH THE INFINEON EASY UTAH BOARD
DEBUGGING WITH THE NMI (NON-MASKABLE INTERRUPT)
DECLARING 2 VARIABLES AT THE SAME ADDRESS
DECLARING BDATA AND SBIT VARIABLES
DECLARING BDATA AND SBIT VARIABLES
DECLARING BITS IN THE SAME BYTE
DECLARING EXTENDED DATA AND BITS
DECLARING EXTERNAL SBITS
DECLARING VARIABLES IN HEADER FILES
DEFAULT PAGELENGTH IS 68, NOT 60
DEFAULT STARTUP AND INITIALIZATION CODE
DEFINE DIRECTIVE
DEFINE DIRECTIVE
DEFINING A STRING ON THE COMPILER COMMAND LINE
DEFINING NEW INSTRUCTIONS WITH MACROS
DEFINING THE MINIMUM STACK SIZE
DESCRIPTION OF ERROR MESSAGES
DETECT OVERWRITES ON LOCAL VARIABLES
DETECTING NULL POINTER ASSIGNMENTS
DETECTING STACK OVERFLOWS
DETECTING UNUSED INTERRUPTS
DETERMINE THE CURRENT RUNNING TASK
DETERMINING PROGRAM SIZE AT RUN-TIME
DETERMINING THE LOCATION OF ASSEMBLER INSTRUCTIONS
DEVICE MAY FAIL AT HIGH CLOCK SPEEDS
DEVICE MAY HAVE NO BOOTLOADER
DEVICE PROGRAMMING WITH HEX FILES
DIFFERENCE BETWEEN CA251 AND DK251 V2.12A UPDATES
DIFFERENCE BETWEEN IF AND $IF
DIFFERENCE BETWEEN INTERVAL AND TIMEOUT
DIFFERENCE BETWEEN ISP AND IAP
DIFFERENCE BETWEEN K_IVL AND K_TMO
DIFFERENCE BETWEEN PK161 AND PK166
DIFFERENCE BETWEEN SFR AND VTREG
DIFFERENCE ISR AND OS FUNCTIONS
DIFFERENCES BETWEEN #INCLUDE <FILE> AND "FILE"
DIFFERENCES BETWEEN C505C AND C515C CAN
DIFFERENCES BETWEEN C51 V7.50 AND V7.50A
DIFFERENCES BETWEEN K_IVL AND K_TMO
DIFFERENCES BETWEEN V3.00 AND V3.00A
DIFFERENCES BETWEEN V4.10 AND V4.10A
DIFFERENCES BETWEEN V6.10 AND V6.10A
DIFFERENT BASIC TYPES ERROR FOR FUNCTION POINTER
DIFFERENT BOARDS
DIRECT ACCESSING OF P2
DIRECTING PRINTF OUTPUT TO SECOND SERIAL PORT
DISABLE CACHE TO AVOID MEMORY READS
DISABLE DIRECTIVE
DISABLE DIRECTIVE
DISABLE WARNINGS ON EC166 EC++ COMPILER
DISABLEWARNING DIRECTIVE
DISABLING ALL INTERRUPTS (EA=0)
DISABLING AUTO-SAVE WHEN BUILDING A PROJECT
DISABLING AUTOMATIC BANK SWITCHING
DISABLING INTERRUPTS IN A FUNCTION
DISABLING INTERRUPTS ON SILICON LABS F12X/F13X DEVICES
DISABLING ROUND-ROBIN PUSHES AND POPS
DISABLING THE OPTIMIZER (FOR VOLATILE VARIABLES)
DISPLAY PROBLEMS WITH FOREIGN LANGUAGES
DISPLAY TMS470 PERIPHERALS
DISPLAYING PERIPHERALS WITH SYSTEM VIEWER
DISPLAYING RTX KERNEL VIEWER
DISPLAYING SPI DIALOG STOPS DEBUGGER
DISPLAYING VTREGS
DIVISION DOESN'T WORK
DIVISION PROBLEMS WITH THE DALLAS 390 / DALLAS 400
DMA FAILS ON SD/MMC INTERFACE
DMA interface on PL330 AXI DMA Controller
DO ARM PERIPHERALS HALT DURING BREAK?
DO I NEED AN INTERNET CONNECTION TO GET A LICENSE?
DO PERIPHERALS STOP WITH ULINK DEBUGGING
DO THE C166 TOOLS SUPPORT THE SIEMENS C164?
DO THE KEIL TOOLS WORK WITH ALL 8051 CHIPS?
DO WHILE STATEMENT
DO XDATA AND CODE MEMORY OVERLAP?
DOCKING WINDOW STYLE
DOCUMENTATION FOR MCB900 V4 IS MISSING
DOES A FLOATING LICENSE REQUIRE A FILE SERVER?
DOES A HARDWARE CHANGE REQUIRE A NEW LIC?
DOES ENUM TYPE CHECKING WORK?
DOES ISD51 WORK WITH THE DALLAS 390, 5240, OR 400?
DOES MCBX51 REPLACE MCB251?
DOES NOT CONNECT, "CANNOT LOAD FLASH PROGRAMMING ALGORITHM"
DOES NOT RUN ON WINDOWS-98/ME
DOES RTX166 FULL PERFORM DYNAMIC STACK SWAPPING?
DOES THE COMPILER COME WITH AN ASSEMBLER?
DOES THE KEIL COMPILER SUPPORT MY CHIP?
DOES THE ORDER DIRECTIVE AFFECT STRUCTURE MEMBERS?
DOES THE RUN-TIME LIBRARY DISABLE INTERRUPTS?
DOES THE TCP/IP LIBRARY SUPPORT SSL?
DOES ULINK WORK WITH THE UPSD32XX DEVICES?
DOES UVISION2 WORK WITH WINDOWS XP?
DOESN'T SAVE THE DUAL DATA POINTERS
DON'T SEE SOURCE WHEN DEBUGGING
DONGLE REQUIRED FOR PROTECTED UVISION3 KIT?
DOS ERRORLEVEL
DOUBLE FLOATING POINT NUMBER SUPPORT
DOUBLE PRECISION FLOATS TRUNCATED TO SINGLE PRECISION
DOUBLE PRECISION MATH ROUTINES
DOWNLOAD PROGRESS BAR MISSING WITH LX51
DOWNLOAD TO FLASH VS. UPDATE TARGET OPTIONS
DOWNLOADING ATMEL 89C51RD2 DEVICES
DOWNLOADING FLASH TO TMS470 TARGETS
DOWNLOADING GNU SOURCE CODE
DOWNLOADING HEX FILES
DOWNLOADING MON390 INTO THE TINI BOARD USING MDK
DOWNLOADING WITH ST-LINK
DOWNLOADING WITH THE LUMINARY DRIVER
DP, DS AND DL DIRECTIVES
DRAG BOXES WITH MULTIPLE VIDEO DISPLAYS
DRIVER PROBLEM GIVES NO USB DEVICE FOUND
DS-5 applications fail to run on security enhanced Linux
DS-5 cannot connect to a core with a very slow clock / Can I stop the core clock when debugging with RVI/DSTREAM units ?
DS-5 debugger fails to connect to PandaBoard over JTAG
DS-5 is showing gdbserver errors when I try to debug my Android native library
DS5000 REAL-TIME CLOCK EXAMPLE CODE
DS80C320.H INCLUDE FILE IS INCORRECT
DS80C390 ARITHMETIC ACCELERATOR
DS80C400 CONTIGUOUS MODE DOES NOT WORK
DS87C520 VS 8051
DSP LIBRARY FOR XC16X MAC UNIT
DSTREAM and RealView ICE (RVI) Code Sequence Information
DTC INTERFACE NO LONGER WORKS
DUAL CAN SUPPORTED
DUAL DATA POINTER PERFORMANCE INCREASE
DUAL DATA POINTER SIMULATION SUPPORT
DUAL DATA POINTERS AND CYPRESS EZ-USB
DUAL DATA POINTERS AND PHILIPS
DUAL DATA POINTERS FOR DALLAS PARTS
DUMMY INTERRUPT SERVICE ROUTINES
DUPLICATE BREAKPOINTS W/TRISCEND TE5_UV2.D
DUPLICATE DECLARATION IN INCLUDE FILE
DYNAMICUSRSTK DIRECTIVE
Damaged installations
Debug and Flash download problems with J-Link
Debugger says 'Can't stop processor'
Debugger shows '*** Data Abort ***' in the execution window
Debugging a non-RM enabled application using the rm.axf demo
Definition of CLKCHANGE / TSCLKCHANGE
Describe late-arriving interrupt behaviour
Design Sign-off Model (DSM) does not function correctly in simulation.
Detecting data accesses or accesses to a range of addresses with AXD and Multi-ICE
Development Boards Fault Report Form
Device Server fails to read or write a file
Dhrystone and MIPs performance of ARM processors
Diagnostic messages A1745W, A1477W and A1786W on use of SP
Difference of behavior between Cortex-M7 and Cortex-M3/M4 or Cortex-M33 around event registering when in SLEEP mode.
Differences between the two versions of Multi-ICE hardware
Discrepancies in ETM-M3 and ETM-M4 programming versus the ETMv3 Architecture Specification
Discrepancy between TRM and PL081 Technical Support Knowledge Article over TransferSize
Displaying Graphic Files Using FlashFS
Do ARM development tools sold at academic pricing come with support?
Do ARM supply a Linux reference driver for PL330?
Do ARM's development tools support BORROW licenses?
Do Cortex-A5 cache evictions generate INCR burst type transfers ?
Do Cortex-M7 and ETM-M7 support system stalling?
Do DSTREAM / RVT2 / RVT units support 'Demultiplexed' trace port mode?
Do I need Level 1 memory if I have zero wait-state memory on the bus?
Do I need TDT?
Do I need any RAM on my target to connect with a debugger? What is a 'Code Sequence'?
Do I need to connect DBGRQ and DBGACK to the 20-pin JTAG connector?
Do I need to connect DSTREAM/RVI to a working target to see it in the network?
Do I need to connect nSRST to the 20-pin JTAG connector?
Do I need to connect nTRST to the 20-pin JTAG connector?
Do I need to implement byte-write access on the ITCM?
Do I need to keep the clock running when the reset line is asserted?
Do I need to run all four cores on CT11MPCore?
Do I need to upgrade my license server if I upgrade my ARM development tools?
Do RVD and RVI support CEVA digital signal processors?
Do RVDS floating licenses support license queuing/wait for license?
Do armcc and armclang provide memory barrier intrinsics?
Do the instruction, peripheral or DMA ports generate unaligned transfers ?
Do the test vectors check the TAP controller ID code?
Do upgrade/update seats replace existing seats?
Does ARM Compiler support inline assembler and embedded assembler for ARMv8?
Does ARM offer dongle based licenses?
Does ARM provide drivers for the USB controller on my development board?
Does ARM provide support for Eclipse?
Does ARM support the use of virtual machines as license servers for ARM software tools?
Does Cortex-M3 Support Coprocessors?
Does Cortex-M3 need Memory Barrier instructions?
Does Cortex-M3 or Cortex-M4 provide status information to distinguish between cold and warm reset?
Does DMC-400 perform sub-word writes atomically?
Does DS-5 support all flavours of Linux?
Does ETB11 support ETM7 and ETM9?
Does ISSM support trace?
Does Mali-200 have hardware to implement bitblit?
Does PL022 support dynamic switching between master and slave?
Does PL111 implement a power-saving mode?
Does PL190 synchronize nIRQ / nFIQ?
Does PL330 support Byte transfers?
Does PL330 wait for a 'ready' signal when executing a DMASTP instruction?
Does PL351 IP support simultaneous program/erase operation with multi-plane NAND devices?
Does PL351 supports RANDOM PAGE READ commands when in NAND boot mode?
Does RVCT for BREW/BREW Builder support C++?
Does RVCT for BREW/BREW Builder support big-endian compilation?
Does RVD support Multi-ICE / RDI connections?
Does RVD support trace points on the Cortex-M3?
Does RVI support ARMv8 processors ?
Does a master always have to perform the write portion of an exclusive access?
Does a master need to issue non-LOCKed accesses when accessing a sequence of AHB slaves ?
Does adding an Embedded Trace Macrocell (ETM) reduce processor performance?
Does armlink support extern "C++" syntax in symbol versioning script files?
Does my ARM DSM model work with Questasim?
Does my Cortex-M3 or Cortex-M4 processor support Multi-drop Serial Wire Debug?
Does my license support multi-core debug in RVD?
Does the AHB Arbiter require address lines as input?
Does the ARM Compiler treat a "plain" int bitfield as a signed int bitfield or as an unsigned int bitfield?
Does the ARM Profiler support big endian targets?
Does the ARM Profiler support profiling NEON/VFP code?
Does the ARM720T with AHB wrapper use halfword or byte burst transfers? (Rev 0-3)
Does the ARM720T with the cache disabled behave like an ARM7TDMI?
Does the ARM7EJ-S support logical equivalence?
Does the ARM926 support RETRY response from a slave?
Does the Cortex-M3 ETM support Cycle-Accurate Trace?
Does the Cortex-M3 support ARM code?
Does the Cortex-R4 support pre-loading of code from main memory into the Instruction Cache?
Does the DSM model the test scan chains?
Does the EB support USB 2.0 Hi-Speed?
Does the EB work straight out of the box?
Does the PL301 support locked transactions from AHB masters?
Does the UART PL011 support the 16c750 standard?
Does the exclusive access local address monitor hold the address of the access ?
Does the source transfer size have to equal the destination transfer size?
Does the timing description of the ARM720T include arcs for when the device is selected as a slave for TIC testing?
Does using the ARM720T FASTBUS mode give significant performance improvement?
Dual Processor PCs and uVision
During AMBA test some signals toggle unpredictably. Why is this?
During our simulation we see a hold time violation on nIRQ relative to BCLK. Is it worth synchronizing nIRQ (and nFIQ) to BCLK externally? What happens when the ARM720T is running off FCLK?
During simulation we found that the AHB Wrapper HTRANS signal changes both on positive and negative clock edges, but the AHB is a single edge protocol. Why does the wrapper do this? (Rev 0-3)
EB Boot Monitor reports '%DiskOnChip-Error, flBadFormat'
EC++ EXCEPTION CODE
EDITOR MESSAGE: LINES LONGER THAN 2048 CHARACTERS
EFFICIENT CODE FOR BYTE ACCESS CONVERSION TO LONG
EJECT DIRECTIVE
EJECT DIRECTIVE
ELIMINATING 16-BIT POINTER INCREMENTS
EMAIL NOTIFICATION OF UPDATES
EMBEDDING COMMENTS IN A COMMAND FILE
EMOV ASM INSTRUCTION FOR THE PHILIPS MX
EMPTY RELOCATABLE SEGMENT
EMPTY SECTIONS ENCOUNTERED
EMULATION AND PROGRAMMING ADAPTERS
EMULATOR LOADER PROBLEMS
ENABLING PL/M-51 SUPPORT
ENABLING THE SOURCE BROWSER
ENABLING XBUS PERIPHERALS
ENUM EXAMPLES
ENUM TYPE CHECKING
ENVIRONMENT VARIABLES AND USES WITH KEIL TOOLS
ENVRIONMENT VARIABLES FOR BUILD PROCESS
EPM900 NOT RESPONDING AFTER ISP PROGRAMMING
ERASE FAILED WITH XC864 AND XC866-1F DEVICES
ERASING/PROGRAMMING EXTERNAL FLASH
ERROR 1 (ILLEGAL CHARACTERS IN NUMERIC CONSTANT)
ERROR 2 (MISSING STRING TERMINATOR)
ERROR 3 (ILLEGAL CHARACTER)
ERROR 4 (BAD INDIRECT REGISTER IDENTIFIER)
ERROR 5 (ILLEGAL USE OF A RESERVED WORD)
ERROR 5 (ILLEGAL USE OF A RESERVED WORD)
ERROR 6 (DEFINITION STATEMENT EXPECTED)
ERROR 7 (LABEL NOT PERMITED)
ERROR 8 (ATTEMPT TO DEFINE AN ALREADY DEFINED LABEL)
ERROR 9 (SYNTAX ERROR)
ERROR 'SARMCM3.DLL' NOT FOUND
ERROR ( TARGET HAS NO OBJECT MODULES )
ERROR (CAN'T READ RETVAL FILE)
ERROR (CANNOT WRITE MEMORY)
ERROR (FAILED TO CREATE WINRUN PARAMETER FILE)
ERROR (NO ALGORITHM FOUND FOR ADDRESS...)
ERROR (UNDEFINED REFERENCE TO ...)
ERROR (UNKNOWN RECORD TYPE)
ERROR (UNKNOWN RECORD TYPE)
ERROR (WRONG CONFIGURATION OF BOOTSTRAP)
ERROR - MISSING DEVICE
ERROR 101 (SECTION COMBINATION ERROR)
ERROR 107 (ADDRESS SPACE OVERFLOW)
ERROR 110 (CANNOT FIND SECTION OR REGBANK)
ERROR 110 (CANNOT FIND SEGMENT)
ERROR 118 (ERRONEOUS REFERENCE TO EXTERNAL VARIABLES)
ERROR 121 (IMPROPER FIXUP)
ERROR 121 (IMPROPER FIXUP)
ERROR 121 (IMPROPER FIXUP)
ERROR 121 (IMPROPER FIXUP) WITH ROM(SMALL)
ERROR 124 (INTERRUPT NUMBER ALREADY USED)
ERROR 125 (DUPLICATE TASK NUMBER)
ERROR 126 (TASK WITH PRIORITY 3 ...)
ERROR 127 (TASK REQUIRES REGISTERBANK 0)
ERROR 127 (UNRESOLVED EXTERNAL SYMBOL) FROM LINKER
ERROR 128 (ILLEGAL PRIORITY FOR TASK)
ERROR 129 (ILLEGAL TASKID: RTX-51 TINY ...)
ERROR 134 (SEGMENT DOES NOT FIT IN PDATA PAGE)
ERROR 141 (TOO MANY INITIALIZERS)
ERROR 146 (INVALID BASE ADDRESS)
ERROR 155 (INVALID BASE ADDRESS)
ERROR 155 (INVALID BASE ADDRESS) IN V3.05E
ERROR 155 (INVALID BASE ADDRESS) IN V4.00
ERROR 166 (ARRAY OF FUNCTIONS)
ERROR 167 (DECLARATION/ACTIVATION ERROR) FOR _MMOV_
ERROR 185 (ATOMIC #5 OUT OF RANGE)
ERROR 200 (LEFT SIDE OF '.' REQUIRES STRUCT/UNION)
ERROR 21 (EXPRESSION WITH FORWARD REFERENCE)
ERROR 216 (OUT OF MEMORY)
ERROR 22 (EXPRESSION TYPE DOES NOT MATCH INSTRUCTION)
ERROR 22 (NO CODE AT ADDRESS 0045H) USING EZ-USB
ERROR 22 (NO CODE MEMORY AT ADDRESS ????H)
ERROR 230 (UNKNOWN STRUCT/UNION/ENUM TAG)
ERROR 258 (MSPACE ILLEGAL IN STRUCT/UNION)
ERROR 26 (CANNOT WRITE INTERRUPT VECTOR)
ERROR 274 (ABSOLUTE SPECIFIER ILLEGAL)
ERROR 45 (UNDEFINED SYMBOL (PASS-2))
ERROR 57: ILLEGAL ADDRESS IN DEBUGGER OUTPUT WINDOW
ERROR 59 WHEN UPDATING FLASH
ERROR 65 (ACCESS VIOLATION)
ERROR 65 USING REMAP FEATURE ON ARM
ERROR 65 WHEN USING MEMMAP ON PHILIPS LPC2000
ERROR 71 (EXPRESSION WITH FORWARD REFERENCE)
ERROR A14 (BAD RELOCATABLE EXPRESSION)
ERROR A14: IS SUBTRACTION IMPOSSIBLE?
ERROR A17 (INVALID BYTE BASE IN BIT ADDRESS EXPRESSION)
ERROR A25 (SYMBOL REDEFINITION)
ERROR A44 (NO CURRENTLY ACTIVE SECTION)
ERROR A74 (OPERAND TYPE MISMATCH)
ERROR C1 (MISPLACED PRIMARY CONTROL LINE)
ERROR C102 (DIFFERENT CONST/VOLATILE...) USING SBIT
ERROR C11 (INTERNAL ERROR)
ERROR C202 USING XBYTE ABSOLUTE ADDRESSING
ERROR C249 (SPECIAL INITIALIZATION EXCEEDS 8K)
ERROR C267 ('FUNCTION': REQUIRES ANSI-STYLE PROTOTYPE)
ERROR INSTALLING TO A 64-BIT OPERATING SYSTEM FROM KEIL CD
ERROR L103 (EXTERNAL ATTRIBUT DO NOT MATCH PUBLIC)
ERROR L104 (MULTIPLE PUBLIC DEFINITIONS) OF MAIN
ERROR L107 (ADDRESS SPACE OVERFLOW)
ERROR L107 (ADDRESS SPACE OVERFLOW) FOR ?STACK
ERROR L107 (ADDRESS SPACE OVERFLOW) WITH INLINE ASM
ERROR L121 (IMPROPER FIXUP)
ERROR L121 (IMPROPER FIXUP) IN STARTUP.A51
ERROR L127 (UNRESOLVED EXTERNAL SYMBOL ?C?CILDPTR)
ERROR L133 (SFR SYMBOL HAS DIFFERENT VALUES)
ERROR L234 (USE RTX-51 CONTROL)
ERROR L235 (USE RTX-166 CONTROL)
ERROR L235 (USE RTX-251 CONTROL)
ERROR L257: EXTENDED LINKER REQUIRES UPGRADE TO PK51
ERROR L6218E: UNDEFINED SYMBOL OS_FIFO
ERROR MESSAGES POINT TO THE WRONG SOURCE LINE
ERROR R210 ON LICENSE CHECKOUT
ERROR/WARNING ON SYMBOL DEFINITION
ERROR: CMSIS_DAP.DLL is missing
ERROR: L6200E: SYMBOL __STDOUT MULTIPLY DEFINED
ERROR: L6218E: UNDEFINED SYMBOL OS_ERROR
ERROR: L6985E WHEN USING __AT DIRECTIVE
ERROR: SARMCR4.DLL NOT FOUND DOWNLOADING OR DEBUGGING
ERRORS ASSEMBLING CONF_TNY.A51
ERRORS ASSEMBLING STARTUP.A51
ERRORS ASSEMBLING XBANKING.A51
ERRORS IN DOUBLE ARITHMETIC
ERRORS IN RTXCONF.A51 AND RTXSETUP.DCL
ERRORS LAUNCHING USER PROGRAMS
ERRORS OPENING HELP FILES
ERRORS USING SBITS AND SFRS
ERRORS WHEN LINKING C++ PROGRAMS
ERRORS WITH IN-LINE ASSEMBLY
ETHERNET INTERFACE FAILS ON A-STEP DEVICES
ETM CONNECTOR FOR MCB2100
ETM CONNECTOR PROBLEM
ETM CONNECTOR PROBLEM
EVAL AND THE FLOATING-POINT LIBRARY
EVAL VERSION "NEEDS TO CLOSE"
EVAL VERSION AFTER INSTALLING WINDOWS MEDIA CENTER
EVALUATION COMPILER FOR CYPRESS EZ-USB FAMILY
EVALUATION COPY
EVALUATION COPY
EVALUATION COPY
EVALUATION KEIL CD REQUIRES SERIAL # FOR INSTALL
EVALUATION SOFTWARE RETURNS ERROR A9932E, C9932E, L9932E OR Q9932
EVEN DIRECTIVE
EXAMPLE GENERIC_8052 RUNS IN X2 MODE
EXAMPLE PROGRAMS
EXAMPLE PROGRAMS FOR THE DALLAS 390 CONTIGUOUS MODE
EXAMPLE PROGRAMS FOR THE PHILIPS MX DEVICES
EXAMPLES FOR EZUSB/ FX /FX2
EXCLUDING FILES FROM A TARGET
EXECUTING FUNCTIONS IN RAM
EXECUTING SPECIAL INSTRUCTIONS IMMEDIATELY AFTER RESET
EXECUTING USER PROGRAMS IN THE BUILD PROCESS
EXECUTION OF SPECIAL INSTRUCTIONS WITH OPTIMIZE 3
EXECUTION ORDER OF TASKS
EXITING SCANF WHEN NO SERIAL DATA IS READY
EXPANSION BUFFER OVERFLOW ERROR
EXPECT LCALL BUT SEE LJMP
EXPECTED DELIMITER ')' AFTER ARGUMENT (INCDIR)
EXPORTING SYMBOLS FOR EMULATORS
EXTENDED SCANF ARGUMENT DATA SPACE
EXTERN DECLARATIONS USING _AT_
EXTERN VARS AND INLINE ASSEMBLY
EXTERNAL EXTENDED BIT VARIABLES
EXTERNAL FLASH / RAM DO NOT WORK PROPERLY
EXTERNAL INTERRUPTS 2-5 ON DALLAS 320
EXTERNAL MEMORY ACCESSED FOR DATA MEMORY POINTER
EXTERNAL MEMORY ON NXP LPC22XX DOES NOT WORK
EXTERNAL MEMORY SETTINGS
EXTERNAL SFR ACCESS FOR 8051 PROGRAMS
EXTINS DIRECTIVE
EXTRA BUTTON CREATED WHEN LABEL CHANGES
EXTS PROBLEMS USING THE _ATOMIC_ FUNCTION
EZ-USB STARTUP CODE
Eight-byte Stack Alignment
Error (CMD16-COR97): Failed to load image "foo.so"
Error from target: gator driver version x is different than gator daemon version y
Error: Cannot Write to RAM for Flash Algorithms
Error: Please update GDBServer to v6.8 or later
Example Linux distribution in DS-5 extracts with errors on Windows
Example code for AB926 Vectored Interrupt Controller (PL190)?
Examples of AXD and ADW/ADU/armsd scripts
FAILURE TO HANDLE SBIT AND INLINE ASSEMBLY
FAILURE TO HANDLE SBIT AND INLINE ASSEMBLY
FAQ How do I customize locales with C macros?
FAR DATA POINTER BOUNDARIES
FAR FUNCTION POINTERS FOR PHILIPS MX
FAR VAR _AT_ COMPARED TO CAST VALUE
FASTER INTEGER DIVISION
FATAL ERROR (#PRAGMA--LINE UNKNOWN CONTROL)
FATAL ERROR (CAN'T CREATE WORKFILE)
FATAL ERROR (CAN'T OPEN FILE) WITH C HEADER FILES
FATAL ERROR (CANNOT CREATE FILE)
FATAL ERROR (CANNOT OPTIMIZE FUNCTION)
FATAL ERROR (LIMIT EXCEEDED)
FATAL ERROR (LIMIT EXCEEDED: SOURCE LINE LENGTH)
FATAL ERROR (MORE THAN 256 SEGMENTS)
FATAL ERROR 204 (INVALID INPUT FILE)
FATAL ERROR 204 (INVALID KEYWORD)
FATAL ERROR 210 (RTX51.LIB NOT FOUND)
FATAL ERROR 210 (RTX51.LIB NOT FOUND)
FATAL ERROR 213 (I/O ERROR ON WORKFILE)
FATAL ERROR 214 (INPUT PHASE ERROR)
FATAL ERROR 228 (RAMSIZE OUT OF RANGE)
FATAL ERROR 232 (...TOO MANY RECURSIONS)
FATAL ERROR 232 (APPLICATION CONTAINS ... RECURSIONS)
FATAL ERROR 250 (CODE SIZE LIMIT)
FATAL ERROR 250 (CODE SIZE LIMIT...)
FATAL ERROR 250 (CODE SIZE LIMIT...)
FATAL ERROR L210 (I/O ERROR ON L51_BANK.OBJ)
FATAL ERROR L220 (INVALID INPUT MODULE) W/TRISCEND E5
FATAL ERROR L251 (CODE SIZE LIMIT)
FATAL ERROR L251 (RESTRICTED MODULE IN LIBRARY)
FATAL ERROR WHEN USING #PRAGMA SRC
FATAL ERRORS AFTER UPGRADING
FILE CHANGED OUTSIDE EDITOR NOTIFICATION
FILE FORMAT FOR 'COVERAGE SAVE'
FILE HISTORY AND RUN PROGRAMS
FILE TYPES FOR COLOR SYNTAX HIGHLIGHTING
FILES OPEN IN READ-ONLY MODE
FILL MEMORY WITH CONSTANT BEFORE LOAD
FILL UNUSED FLASH CONTENT WITH PREDEFINED VALUE
FILLING UNUSED INTERRUPT VECTORS WITH SJMP $
FIND FUNCTION FAILS WHEN SWITCHING SOURCE FILES
FIND IN FILES DIALOG OPEN SLOWLY
FIND WORKS DIFFERENTLY IN µVISION3
FINDING ASSEMBLER INCLUDE FILES
FINDING THE END OF THE BINARY
FIXBFLD DIRECTIVE
FIXDRK DIRECTIVE
FIXPEC DIRECTIVE
FIXUP ERROR IN LIBRARY WITH MERGEPUBLICS
FLASH ALGORITHM FOR PHILIPS DEVICES
FLASH DOESN'T ALWAYS LOAD
FLASH DOWNLOAD FAILS WITH STM UPSD DEVICES
FLASH DOWNLOAD FOR SEGGER JLINK FAILS
FLASH DOWNLOAD NOT WORKING
FLASH DOWNLOAD OF NXP LPC17xx FAILS
FLASH DOWNLOAD WITH ULINK FAILS WITH VERIFY ERROR
FLASH DOWNLOAD WITH ULINK2 FAILS
FLASH DOWNLOADING WITH CORTEX-M3 DRIVER
FLASH LOADER WITH BATCH MODE
FLASH MEMORY ON THE ADUC812
FLASH MUST START AT 0XC00000
FLASH PROGRAMMING - NO ALGORITHM FOUND
FLASH PROGRAMMING FAILS ON LUMINARY EVAL BOARD
FLASH PROGRAMMING OF PHILIPS LPC2000 FAILS
FLASH PROGRAMMING UTILITIES
FLASH TIMEOUT ON LUMINARY DEVICES
FLASH VERIFY ERRORS WITH INFINEON XC866
FLASHING FROM A FILE DIFFERENT THAN THE PROJECT OUTPUT
FLASHMON CRASHES WHILE LOADING ON ATMEL DEVICE
FLEXnet lmgrd daemon not found on Ubuntu
FLEXnet/FLEXlm Windows Node-locked licence check fails after installing Model Networking
FLOAT64 DIRECTIVE
FLOATFUZZY DIRECTIVE
FLOATFUZZY DIRECTIVE
FLOATFUZZY DIRECTIVE
FLOATING LICENSE USERS DO NOT DISPLAY
FLOATING LICENSE: NAME NOT DISPLAYED
FLOATING POINT LIBRARY ROUTINES REGISTER USAGE
FLOATING-POINT REENTRANCY IN ISR?
FLOATING-POINT STANDARD
FLOATING-POINT SUPPORT
FLOWCHARTING SOFTWARE
FONTS AND PRINTING
FOR STATEMENT
FORCE A VALUE TO AN SFR FROM THE DEBUGGER
FORMAT OF ?C_INITSEG SEGMENT
FORMAT OF __DATE__ MACRO HAS CHANGED
FORMFEEDS IN LISTING FILES
FORWARD STRUCTURE REFERENCES IN C
FS2 DEBUGGER DOES NOT CONNECT
FULL VERSION BEHAVES AS EVAL VERSION
FULL VERSION OF TOOLS SHOW CODE SIZE LIMIT
FUNCTION OF ?C?ICALL AND ?C?ICALL2
FUNCTION POINTER VALUES DIFFER IN THUMB MODE
FUNCTION POINTERS IN CONTIGUOUS MODE
FUNCTION POINTERS, CODE BANKING, AND NOOVERLAY
FUNCTION PROTOTYPES FOR REENTRANT FUNCTIONS
FUNCTIONAL PROBLEM CPU.12
FUNCTIONS DIRECTIVE
FUNCTIONS THAT ARE REENTRANT
Fatal Error: The processor failed to re-enter debug state after a system speed access
Features and performance of ARM Test Chips are subject to change
Flash Magic: Parameter-Settings with PK51
Flow Control: Why would a peripheral be used as the flow controller in preference to the DMAC?
GAPS IN DATA SPACE
GENERAL PURPOSE SFR INTERFACE
GENERAL TCP/IP QUESTIONS
GENERAL: INSTALLED PRODUCTS AND VERSION INFORMATION
GENERATE ENWDT INSTRUCTION
GENERATING A CALL TO AN ABSOLUTE MEMORY LOCATION
GENERATING A LIBRARY FOR GENERIC DEVICES
GENERATING A ROM CHECKSUM
GENERATING BINARY OUTPUT DURING A BUILD
GENERATING HEX FILES FOR BANKED APPLICATIONS
GENERATING HEX FILES FOR CODE BANKING PROGRAMS
GENERATING HEX FILES FOR PHILIPS MX DEVICES
GENERATING HEX FILES WITH EVEN NUMBER OF BYTES
GENERATING INSTRUCTIONS USING CERTAIN ADDRESSING MODES
GENERATING INTERRUPTS IN SIMULATION SCRIPT
GENERATING MORE THAN ONE LIBRARY
GENERATING OBJECT FILES IN SPECIFIC FOLDERS
GENERATING PUSH AND JMP INSTEAD OF CALL INSTRUCTIONS
GENERATING THE DIVL INSTRUCTION
GENERATING USER EXCEPTIONS FOR XDATA
GET "CAN'T EXECUTE..." RUNNING BIN2HEX PGM
GET "NO LICENSE AVAILABLE" AFTER LICENSING
GET "RENEW LICENSE ID CODE" ADDING LIC
GET ERROR 108 DOWNLOADING PRODUCT UPDATE
GET ERROR A45: USING IN-LINE ASSEMBLER
GET R20E ERROR WHEN ADDING LIC
GET SARM.DLL NOT FOUND DURING INSTALL
GETCHAR ECHOS CHARACTERS
GETS R206 ERRORS UNDER VISTA OR WINDOWS 7
GETTING ALIGNMENT WARNING A134 ON ASSEMBLY
GETTING COMPILER VERSION NUMBER
GETTING DEFINED VALUE FROM THE COMMAND LINE
GETTING ERROR A0594E WITH EVAL MDK-ARM VERSION
GETTING EVAL VERSION USING SILABS IDE
GETTING FS2KEIL51.DLL NOT FOUND
GETTING INLINE ASSEMBLY TO WORK
GETTING INTERRUPTS WORKING
GETTING MANUALS
GETTING PROGRAMS ONTO A TARGET BOARD
GETTING STARTED
GETTING STARTED BOOK FOR C51
GETTING THE CODE BANK OF A FUNCTION
GETTING THE CURRENT BANK NUMBER
GLOBAL OR STATIC VARIABLES NOT BEING INITIALIZED
GLOBAL REGISTER VARIABLES IN ASSEMBLY
GLOBAL VARIABLE PROBLEM WITH DALLAS 390 CONTIGUOUS MODE
GOTO MATCHING BRACE DOESN'T WORK
GOTO STATEMENT AND LABELS
GPF WHEN OPENING OLD C166 PROJECT
GPIO PIN OUTPUT
GREY CHECK BOXES IN FILE AND GROUP OPTIONS
General : What system support is required if a slave can be powered down or have its clock stopped?
General : When can Early Burst Termination occur
General questions about Versatile logic tiles
General questions about the PB926
General questions relating to all Integrator boards
General: Can HTRANS change whilst HREADY is low?
General: Can a BUSY transfer occur at the end of a burst?
General: Can a master change the address/control signals during a waited transfer?
General: Can an AHB master be connected directly to an AHB slave?
General: Do all slaves have to support the BUSY transfer type?
General: Does the address have to be aligned, even for IDLE transfers?
General: How many masters can there be in an AHB system?
General: How should AHB to APB bridges handle accesses that are not 32-bits?
General: Is HREADY an input or an output from slaves?
General: Is a default slave really necessary?
General: Is a dummy master really necessary?
General: Is it legal for a master to change HADDR when a transfer is extended?
General: Is it specified that HPROT, HSIZE and HWRITE remain constant throughout a burst?
General: The specification recommends that only 16 wait states are used. What should you do if more than 16 cycles are needed?
General: What are the different bursts used for?
General: What default state should be used for the HREADY and HRESP outputs from a slave?
General: What is a default slave?
General: What is the difference between a dummy bus master and a default bus master?
General: What is the recommended default value for HPROT?
General: What is the state of the AHB signals during reset?
General: What sequences of transfers types (HTRANS) can occur on the bus?
General: When a master rebuilds a burst which has been terminated early are there any limitations on how it rebuilds the burst?
General: Why is a burst not allowed to cross a 1 kilobyte boundary?
General: Why is there no wait signal on the APB?
Get "No Synchronization" Using SWO on SI3MU1xx Board
HALT BUTTON DOES NOT STOP SIMULATOR EXECUTION
HALT BUTTON DOES NOT STOP SIMULATOR EXECUTION
HALT BUTTON DOES NOT STOP SIMULATOR EXECUTION
HALTING EXECUTION IN A SIGNAL FUNCTION
HANDLING UNUSED INTERRUPTS
HANDLING UNUSED INTERRUPTS
HANGS AT SPLASH SCREEN
HARDWARE REQUIREMENTS
HARDWARE TIMER INTERRUPT FAILS
HARVARD VS VON NEUMANN
HAS CARM BEEN REMOVED FROM MDK-ARM?
HEADER FILE FOR THE PHILIPS 87C554
HEADER FILE IS BEING PROCESSED MORE THAN ONCE
HELLO EXAMPLE DOES NOT WORK
HEX CODE WITHOUT ADDRESSES
HEX FILE NOT CREATED
HEX FILE NOT CREATED MESSAGE
HEX FILE NOT GENERATED
HEX FILE SIZE IS TOO LARGE
HEX FILE START AND END ADDRESSES HAVE NO EFFECT
HEX OUTPUT FILE FOR A DEVICE PROGRAMMER
HEX PROGRAMMING APPENDS .AXF?
HID CLIENT EXAMPLES
HLDEN BIT CLEARED BY OS
HOLD DIRECTIVE
HOW ARE FUNCTION PARAMETERS HANDLED?
HOW BIG CAN A BINARY NUMBER BE?
HOW CAN I LOG VARIABLE VALUES TO A FILE
HOW CAN I REQUEST PRODUCT INFORMATION
HOW CAN I SET THE PROGRAM COUNTER IN C OR ASSEMBLY?
HOW CAN I USE UVISION WITH ST-CAPS
HOW COMPATIBLE IS THE 251 WITH THE 8051?
HOW DO I DELETE KEIL TOOLS FROM MY COMPUTER?
HOW DO I PROGRAM THE ON-CHIP FLASH
HOW DO I READ A LATCH?
HOW DO I REMOVE AMAKE RECORDS FROM MY OMF FILE?
HOW DO I USE INLINE ASSEMBLY
HOW DOES OVERLAY ANALYSIS WORK?
HOW FAST IS THE 251?
HOW MUCH CODE AND DATA ARE USED?
HOW MUCH MEMORY IS USED BY MY PROGRAM?
HOW MUCH RAM IS REQUIRED?
HOW QUICKLY ARE INTERRUPT TASKS EXECUTED?
HOW TO ACCESS AX88796 EMBEDDED PHY REGISTER
HOW TO ANALYZE A DATA ABORT EXCEPTION
HOW TO AVOID STEPPING INTO INTERRUPTS
HOW TO CONFIGURE
HOW TO CONNECT TWO PORT PINS
HOW TO COPY A PROJECT
HOW TO CREATE ASSEMBLY FILES FROM C FILES
HOW TO CREATE ASSEMBLY FILES FROM C FILES
HOW TO CREATE ONE HEX FILE FOR MY APPLICATION
HOW TO DIRECTLY ADDRESS MULTIPLE CONSECUTIVE SFRS
HOW TO FIND THE UVISION INSTALLATION PATH
HOW TO GET 16-BIT ADDRESSES INTO THE PEC REGISTERS?
HOW TO GIVE DESCRIPTIVE NAMES TO PORT PINS
HOW TO LOAD PEC REGISTERS OF XC16X DEVICES
HOW TO LOCATE INTERRUPT SERVICE ROUTINES FOR STR71X
HOW TO RE-ENABLE JTAG ON LPC21XX DEVICES
HOW TO RETAIN DATA IN OBJECT FILE
HOW TO SERVICE A WATCHDOG TIMER WHEN USING THE SD FILE SYSTEM
HOW TO SET THE ULINK VCC JUMPER
HOW TO STRUCTURE MODULES IN A LIBRARY
HOW TO UPDATE THE TRISCEND DEBUG DRIVER
HOW TO USE 256 BYTES DATA SPACE
HYPHENS ARE NOT ALLOWED IN INCLUDE FILE FILENAMES
Hardware Fault Report Form
Header file searching with -I and -J
Hold at reset example
How accurate is the DSM?
How and when should I use the 64-bit version of the ARM linker?
How are CDBGRSTREQ and CDBGRSTACK used?
How are Memory Type and Memory Attributes represented on the AHB-Lite bus interfaces of Cortex-M3 and Cortex-M4?
How are interrupts routed from the LogicTile Express 13MG?
How are the DBGEXT signals used?
How are the uni-directional data buses in the ARM7TDMI used?
How can I access high memory above 4GB?
How can I access the 720T CP15 registers by JTAG debug sequences?
How can I add a Logic Tile to my Integrator boards?
How can I attach a JTAG device to a JTAG-AP if that device does not generate RTCK ?
How can I build a low-cost development environment for student use?
How can I change the debug control bits in the Debug Status and Control Register?
How can I change the size of the MultiTrace trace capture buffer?
How can I check for Erratum 602117 LDRD opcodes in my Cortex-M3 code image?
How can I check that I've installed the DSM properly?
How can I compile for specific architectural extensions such as Advanced SIMD (NEON) when targeting an ARMv7-A processor?
How can I connect my DSTREAM / RealView ICE directly to my computer with an Ethernet cross-over cable?
How can I control MTI behaviour from a LISA+ component
How can I count the number of instructions executed by the processor in a given time interval?
How can I define memory mapped performance counters in Streamline?
How can I disable JTAG debug?
How can I enable full debug console output in Node Emulator?
How can I enable interrupts on the CT926?
How can I enable the ETM interface signals of Cortex-M4 or Cortex-M4?
How can I ensure that WFE causes sleep?
How can I exposing SystemC resources via CADI
How can I generate LOCKed, Exclusive and burst transfers on ARM926 and ARM1176 cores?
How can I generate a simple page table for the ARM720T, so that I can turn on the MMU?
How can I handle license error from within SystemC
How can I improve the build time of my application?
How can I investigate suspected network problems with my DSTREAM or RVI unit ?
How can I make use of multiple license sources?
How can I modify the Cortex-M0+ Integration Kit MCU example to relocate the MTB into an executable address range?
How can I monitor the signals between the Motherboard and the Logic Tile?
How can I obtain an ARM University Program price list of all the tools on offer at academic rates?
How can I obtain development tool donations from ARM for use in my school?
How can I order a Versatile Family CD?
How can I prevent occasional build failures caused by license management errors when using floating licenses?
How can I protect against stack overflow at run-time?
How can I reconfigure PL340 after reset?
How can I recover from a RVD crash when running automated tests?
How can I replay the ARM7TDMI serial test patterns on the DSM?
How can I simulate stale endpoints in the Device Server Admin UI using Node Emulator?
How can I tell how many licenses are in use?
How can I tell whether the Cortex-M3 is in Thread or Handler mode?
How can I tell which version of TDT is installed?
How can I use Cortex-M3 bit-banding from C code?
How can I use RVD to load my application into flash memory on the Cortex-M3 MPS RTSM model?
How can I use SCADI from a LISA+ component to model a synchronous watchpoint
How can I use a Cortex M3 model as a Cortex M0?
How can I use my own implementation of 'printf()' without needing to recompile my application code?
How can I use the DAP logger tool?
How can I use the SWJIM which comes with Cortex-M3 for my chip-level design?
How can I use workspaces to control RVD's GUI?
How can I view RVISS Tracer output in RVD?
How can I write a LISA+ component that requests a file to load
How can ICSR show a pending interrupt PENDSTSET but no VECTPENDING?
How can a Cortex-M processor wake up from WFI if interrupts are masked or disabled?
How can a slave return a BRESP before knowing the AWADDR value for the transaction ?
How can my software determine the EB PCB revision?
How can software identify one Cortex-M3/4 processor instance in a SoC containing multiple instances?
How can the ARM banked registers be initialized?
How can the ARM926EJ-S perform overlapped transfers
How can the Debugger identify a SoC containing a CoreSight Debug Access Port (DAP)?
How can we calculate the number of test cycles for RAM BIST on ARM1176 ?
How do DSMs handle 'x' values in simulations?
How do Dhrystone results in the Cortex-M3 "example" system compare with those in the Cortex-M4 Integration Kit?
How do I access the symbols in my image using RVD?
How do I add a trace license to ADS?
How do I add bare-metal support for a new target in DS-5?
How do I add scan chains to the ARM TAP controller?
How do I add source files to an existing project in RVD?
How do I avoid the compiler generating LDM/STM instructions?
How do I boot Linux on the A57-SMM?
How do I boot Linux using .dtb files on my Versatile Express system?
How do I boot SMP Linux on the EB RTSM?
How do I boot a Cortex-M3 or Cortex-M4 processor with uninitialized memory at address zero?
How do I build Linux applications with RVCT 3.0 and later?
How do I build and run code for VFP?
How do I calculate the offset address for my flash mounted filesystem on my Versatile Express system?
How do I change clock frequencies on the ARM1136JF-S Core Module?
How do I change clock settings on the EB+CT-R4F?
How do I change clock settings on the PB11MPCore?
How do I change clock settings on the PBX-A9?
How do I change clocks on the Core Tile Express V2P-CA9x4?
How do I change clocks on the Versatile Express Motherboard V2M-P1?
How do I change the CPU and bus frequency on PB-A8?
How do I change the clock frequencies on the CT1136?
How do I change the clock frequencies on the CT926?
How do I check the FPGA build version programmed on my PB development board?
How do I check whether my kernel configuration will work with Streamline?
How do I choose ARM based processors?
How do I completely remove ADS from a machine?
How do I configure DSTREAM/RVI to connect to a target using Serial Wire Debug (SWD)?
How do I configure DSTREAM/RVI to debug cores behind a JTAG-AP in CoreSight systems?
How do I configure Multi-ICE Server to connect to the PB926?
How do I configure NAT networking between Fast Models and an external network on Windows?
How do I configure RVD to match my OKI hardware target?
How do I configure RVD v3.1/RVI v3.1 to capture ETM Trace using the Embedded Trace Buffer (ETB) on the PB1176?
How do I configure RVD v3.1/RVI v3.1 to debug the PB1176?
How do I configure RVD v3.1/RVI v3.2.1 to capture ETM trace using the Embedded Trace Buffer (ETB) on the PB1176?
How do I configure RVD v3.1/RVI v3.2.1 to debug the PB1176?
How do I configure RVD v4.0/RVI v3.3 to capture ETM trace using the Embedded Trace Buffer (ETB) on the PB1176?
How do I configure RVD v4.0/RVI v3.3 to debug the PB1176?
How do I configure RVD_3.1/RVI_3.1 to capture ETM Trace using RVT on the PB1176?
How do I configure RVD_3.1/RVI_3.2.1 to capture ETM Trace using RVT on the PB-A8?
How do I configure RVD_3.1/RVI_3.2.1 to capture ETM Trace using RVT on the PB1176?
How do I configure RVD_4.0/RVI_3.3 to capture ETM Trace using RVT on the Microcontroller Prototyping System (MPS)?
How do I configure RVD_4.0/RVI_3.3 to capture ETM Trace using RVT on the PB1176?
How do I configure RVI and RVD to debug my Cortex-M3?
How do I configure RealView-Debugger to use ETB trace?
How do I configure and debug my CoreSight system using RVD/RVI?
How do I configure semihosting in RVD?
How do I configure semihosting in RVD?
How do I configure the parameters for an ARM946E-S DSM model instance?
How do I configure vector_catch in RVD?
How do I connect ARM Profiler 2.1 to a Fast Models Virtual Platform?
How do I connect DS-5 to a remotely-running Fast Model / specify a different CADI Server port to be used
How do I connect an external PSU to a Multi-ICE that has no DC input jack?
How do I connect external hardware to a LogicTile Express V2F-1XV5 board? Can I stack other boards on top of a LogicTile?
How do I connect multiple ACE-Lite masters to a single CCI-400 ACE-Lite slave interface?
How do I connect to a RTSM with RealView Debugger v3.1 ?
How do I control clock gating?
How do I control memory access size when using RVD / RVI?
How do I create a custom BCD file for my hardware?
How do I customize locales?
How do I diagnose my faulty board?
How do I display Neon instructions in the RVD disassembly view?
How do I display custom coprocessor registers in RVD?
How do I display two memory windows viewing different address locations in RVD?
How do I do conditional execution in A64?
How do I drive FCLK during TIC testing of ARM720T?
How do I dynamically update compile-time configured strings in MDK-Middleware?
How do I dynamically update compile-time options in MDK-Professional Middleware before service initialization?
How do I enable parallel builds within Eclipse?
How do I enable the 64KB page size kernel on ARCH64?
How do I enable/disable semihosting on ISSM and RTSM models?
How do I exit the Flash Memory Control Window in RVD?
How do I export a flash algorithm for RealView Debugger on Linux?
How do I fill unused ROM with specific content?
How do I find my ARM serial number?
How do I find my host ID?
How do I find the Version and Build Numbers for my RVD/RVI tools?
How do I find the version of a model component?
How do I force HW and SW breakpoints in RVD?
How do I generate ARM v6T2 or v7 DSP multiply instructions using the ARM Compiler toolchain?
How do I generate an imprecise abort on the ARM926EJS as part of a test case?
How do I generate interrupts using a SystemC component?
How do I get cycle counts from ISSM?
How do I get my ARM1176 processor to do unaligned accesses without aborting?
How do I get started with AXD and MultiTrace?
How do I get the EIS traces from multiple ARM cores in to different files?
How do I get the best performance when compiling floating point code for Cortex-M4F?
How do I halt execution at the reset vector ?
How do I handle GIC-400 unexpected interrupts on FPGA?
How do I implement an AMBAPV ACE master?
How do I import a cpp model as a shared object?
How do I import hardware platforms using the Platform Configuration Editor in DS-5?
How do I import the DS-5 example projects into Eclipse?
How do I install RVD and RVI on a network drive under Linux?
How do I install my floating license?
How do I install my node locked license?
How do I install the ADS software archive provided with RVDS?
How do I install the RVI-ME drivers for Versatile Boards in Windows 7?
How do I install the pre-built Linux images on my ARM development board?
How do I load and debug a big-endian image using RealView Debugger?
How do I load images into flash with RVD?
How do I load symbols for an image already resident in flash using RVD?
How do I lockdown part of my data cache?
How do I make my VFPv2 code IEEE 754 compliant?
How do I make the Versatile Express Motherboard V2M-P1 switch on when the 12V power is connected?
How do I merge my license files?
How do I move my license to another machine?
How do I obtain logging from the VSTREAM Client ?
How do I obtain my license file?
How do I obtain the V7 Architecture Reference Manuals?
How do I obtain the design data (schematics, pinout, etc) for the Versatile Express family of boards?
How do I obtain the design data for my Versatile boards?
How do I overload operator new?
How do I pass command line arguments to the ISSMs in RVD?
How do I pass command line arguments to the RTSMs in RVD?
How do I perform TPIU trace on the A57-SMM using DS-5?
How do I perform profiling on the CT1176 + EB?
How do I port my application code to my target hardware?
How do I port my project to Microlib?
How do I power down an ACE master that is connected to CCI-400?
How do I prevent uninitialized data from being initialized to zero?
How do I produce a trace Association file to describe my CoreSight systems to RVD/RVIv3.1?
How do I program flash memory with RealView Debugger?
How do I program the FPGA image on my Versatile Board?
How do I rebuild the Linux kernel for my ARM development board?
How do I redirect the semihosting output to a file?
How do I reprogram the Boot Monitor in Flash on my Versatile development board?
How do I reset individual CPUs on the CoreTile Express A15_A7 (TC2)?
How do I reset my Eclipse environment configuration to use default settings?
How do I reset the target processor in RVD?
How do I retarget C++ streamed I/O?
How do I run the "fpu" validation test in my RTL simulation?
How do I run validation for the medium-plus configuration of ETM9?
How do I select RealView-ICE Serial Wire Debug?
How do I set explicit ARM or Thumb Instruction breakpoints in RVD?
How do I set the cache size on my DSM?
How do I set top_of_memory?
How do I set top_of_memory?
How do I silently install DS-5?
How do I specify paths to header files in Projects in RVD?
How do I switch ON/OFF my Versatile Express Motherboard V2M-P1?
How do I switch the debugger connection between JTAG and SWD (Serial Wire Debug) protocol?
How do I switch toolchains in DS-5?
How do I tell how many units (or days) are left during a RVDK for OKI Evaluation?
How do I trace the MCBSTM32E using the CoreSight High Density Probe?
How do I transfer my license to another company?
How do I uninstall System Generator?
How do I update the Eclipse plug-in for RVDS 3.1?
How do I upgrade my Versatile Express and start up the system?
How do I upgrade to a later version of RVDS?
How do I use GDB with a RVI unit to debug my standalone application on an ARM target?
How do I use INCBIN to merge multiple binary images?
How do I use Multi-ICE on a PC with no parallel port?
How do I use RVD Macros?
How do I use SCADI from a MTI plugin
How do I use VFP operations on the RTSM models?
How do I use VRECPE / VRECPEQ for reciprocal estimate?
How do I use a Core Tile on an IM-LT3?
How do I use a Core Tile on an Integrator CP?
How do I use a Core Tile on my own custom motherboard?
How do I use local capture with ARM Streamline?
How do I use the ARMv6 AHB-Lite extension signals in my AMBA 2.0 system?
How do I use the Android adb to forward Gator data over USB?
How do I use the Jazelle DBX engine?
How do I use the PVBusMapper component?
How do I use the SETPEND and CLRPEND registers in Cortex-M3?
How do I use the SMSC Ethernet component?
How do I write code portable between ARM Compiler 5 and ARM Compiler 6 for the __at sections?
How do RVI and MultiICE access memory on a hardware target?
How do the ARM Compilers handle memcpy()?
How do the ARM Compilers handle printf, sprintf, fprintf and scanf?
How do the synchronization primitives work in coherent regions of an MPCore processor
How do we determine the AXI parameters of DMA transfers (particularly the length) ?
How do you calculate addresses used in WRAP type bursts?
How do you connect an AHB Master to an AHB-lite system?
How do you connect an AHB slave to an AHB-lite system?
How do you connect an AHB-lite Master to a full AHB system?
How do you connect an AHB-lite Slave to a full AHB system?
How do you ensure interoperability between AXI components?
How does AHB differ from AHB-lite?
How does Cortex-A5 make use of data linefill buffers 0 and 1 ?
How does Cortex-M3 and Cortex-M4 conform to the ARMv7-M Architecture for Load and Store Exclusives?
How does Cortex-M3 handle 32-bit opcodes not aligned on word boundaries?
How does Little / Big Endian mode affect aligned / unaligned addressing?
How does NIC-301 asynchronous bridge deal with burst transfers?
How does RVD make use of makefiles?
How does RVD/RVI debug affect the contents of my core's caches?
How does __weak work?
How does a SWP operation on a CPU translate in to bus activity?
How does channel arbitration work in PL080?
How does inline in the C99 standard behave differently?
How does the AHB handle LOCKed SPLITs?
How does the ARM Compiler support unaligned accesses?
How does the ARM compiler allow for the configurable multiplier in the Cortex-M0?
How does the ARM11 JTAG synchronisation logic work?
How does the Cortex-A5 automatic data prefetcher work ?
How does the DMIPS/MHz performance vary with wait-states on the code memory?
How does the JTAG synchronisation logic work? / How does adaptive clocking work?
How does the PL340 generate memory address from the AXI address?
How does the compiler handle multiple definitions of global variables?
How does the coprocessor interface of the ARM7TDMI work?
How does the insertion of the AHB wrapper affect the performance of the ARM7TDMI?
How does the interrupt handling latency of the ARM720T compare with ARM7TDMI?
How does the memory controller know whether the current access is aligned/non aligned word/half-word/byte?
How does the sample rate parameter affect profiling on hardware?
How does the switching between BCLK and FCLK work in ARM720T?
How fast are the PB1176JZF-S, PB11MPCore, PB-A8 and PBX-A9 baseboards?
How fast is Integrator?
How fast is the CPU clock on Core Tiles?
How fast is the CT11MPCore + EB platform?
How fast is the EB?
How fast is the PB926?
How flexible is the interrupt and excpetion priority scheme in ARMv7-M?
How important is it that a sequence of locked transactions does not cross a 4k byte boundary?
How is DS-5 Kernel only Trace configured?
How is simultaneous access to the DTCMs by the core / DMA done ?
How is the ARM7TDMI core tested?
How is the JTAG chain routed on the EB?
How is the L2C-310 TAGCLKEN generated for clock ratio 3:1 ?
How many Logic Tiles can I stack on the EB and PB926?
How many clock cycles should the reset signal in an AMBA system be asserted for?
How many cores can I trace at the same time with RealView ICE and RealView Trace?
How many outstanding write transactions are supported by Mali-200? Can Mali-200 support write interleaving?
How much trace can RealView-Trace capture ?
How shold we connect Cortex-A5 to PL310 to assert PL310 idle when CPU is in standby ?
How should ARM7TDMI/ARM9TDMI pins be driven to test the core using serialised test vectors via JTAG?
How should DMAFLUSHP be used?
How should I set the Peripheral ID register values in my CoreSight ROM Table?
How should I write to the System Handler Control and State Register?
How should a 32-bit write accesses across a 64-bit bus be represented as AXI transactions?
How should a bridge deal with an AXI transfer that is marked as non-secure and bufferable?
How should cache maintenance operations be handled in systems with multi-level cache, with reference to DMA?
How should power-on reset be applied to the ARM7TDMI?
How should we initialise the L1 memories and what is the function of L1RSTDISABLE signal ?
How to 'hot-plug' the JTAG with Multi-ICE (post-mortem debugging)
How to access a Cortex-M processor's memory system from my own Debug transactor?
How to change the frequency of the RVI/DSTREAM sampling clock
How to enter the debug state for Cortex-M3
How to generate CLK# pin in PL340 for DDR Memories?
How to implement CADI breakpoints in a LISA component
How to list all the MTI trace sources in your system?
How to re-implement library functions?
How to run Node Emulator in queue mode
How to should I setup my cache modelling in FastModels?
How to solve DS-5 installation issues under Windows?
How to start Device Server to support CoAP over TCP
How to the Fast Models handle active low ports on the cores?
How to trace MTI events on my model
How to troubleshoot the error: Web services unavailable, check network settings
How to use $Super$$ and $Sub$$ for patching data?
How to use mDS with Hazelcast
I CAN NOT VIEW THE CHM HELP FILES USING WINDOWS VISTA/7
I am confused about the PARTNO value in the IDCODE of my CoreSight DAP's Debug Port
I am having trouble with my MDK-ARM, RVDS, or ADS license. What should I do?
I can't find EtmDefs.v
I can't generate a test.bsi file when I compile IK test in big-endian mode
I cannot connect to my MPS board or download images when using the HPE_Desk tool in Windows 7
I cannot find the "Integration and Implementation Manual" (IIM) on infocenter.arm.com
I cannot see my DSTREAM / RealView ICE unit in the network with the RVConfig Browse button
I cannot see my DSTREAM / RealView ICE unit on the network with the RealView ICE Config IP utility
I designed a board to be used with Multi-ICE. Can I use RealView ICE instead?
I don't understand the description of background region priority under PRIVDEFENA in the TRM
I have found some clock domain crossing paths in CoreSight ETM-R4. How do I constrain them?
I turn on the protection unit and I get prefetch aborts
I want code to translate virtual addresses to physical addresses
I want to capture trace in my CoreSight ETB while not clocking the CoreSight TPIU but my trace stalls.
I would like to do an ARM-based school/university project
I would like to do an ARM-based school/university project. Does ARM have any suggestions?
I²C SIMULATION WITH C16X DEVICES
I'm interested in developing coursework around ARM. Where do I start?
I'm not implementing an external coprocessor. How should I tie off the interface?
I'm running my code and I'm getting data aborts
I-Cache, D-Cache and MMU combinations
I/O ERROR ON WORK FILE
I/O PINS DON'T TOGGLE DURING COMMUNICATION
IAP, ISP SUPPORT FOR EPM900
ICP PROGRAMMING OF LPC900 DEVICES
IDATALOOP NEVER ENDS
IDE DOESN'T DETECT LIBRARY MODIFICATIONS
IDENTIFY INSTRUCTION CAUSING CLASS B HARDWARE TRAP
IDLE MODE ON THE ATMEL AT89C1051
IIM description of HMASTERD = 0b10 does not make sense
IM-LT3 nPPRES(0) signal on wrong HDRB pin
IMAGEHLP.DLL FILE IS MISSING
IMPLEMENTATION OF 'BIT' TYPE CASTS
IMPLEMENTING XDATA BANKING
IMPORT SYMBOLS OF A MAIN APPLICATION
IMPORTING A UVISION V1 PROJECT INTO UVISION V2.02
IMPORTING A UVISION V1 PROJECT INTO UVISION V2.04 & LATER
IMPORTING DAVE 2.0 PROJECTS
IMPORTING HEX FILE INTO XDATA MEMORY
IMPROPER FIXUP ON BANKING APPLICATION WITH UNUSED FUNCTIONS
IN-APPLICATION PROGRAMMING (IAP) ON PHILIPS LPC9XX
IN-LINE ASM GIVES COMPILER WARNINGS
IN-LINE ASSEMBLER ACCESS TO SPSR
IN-LINE ASSEMBLER: INVALID EXPRESSION TOKEN
IN-LINE ASSEMBLY GENERATES ERROR C197
IN-SYSTEM FLASH PROGRAMMING (PART 1)
IN-SYSTEM FLASH PROGRAMMING (PART 2)
IN-SYSTEM FLASH PROGRAMMING WITH ROM SIZE > 64KB
IN-SYSTEM PROGRAMMING PROBLEM
INC DRK PROBLEMS WITH THE INTEL 80C251SB
INCDIR DIRECTIVE
INCDIR DIRECTIVE
INCDIR DIRECTIVE
INCLUDE FILE FOR ATMEL 89S8252
INCLUDE FILE FOR DALLAS DS87C550
INCLUDE FILES
INCLUDE FILES IN THE DEPENDENCY CHECK
INCLUDING C SRC FILES IN A PROJECT
INCLUDING OBJECT FILES IN LINK
INCLUDING TEST CODE IN APPLICATIONS
INCOMPATIBLE MOTHERBOARD/USB CHIPSETS
INCOMPATIBLE VERSION OF RPC STUB
INCOMPLETE TASK LIST DISPLAY WITH BIG ENDIAN
INCONSISTENT VALUES ON VOLATILE VARIABLES
INCORRECT ACCESSING OF 2D ARRAY IN STRUCTURE
INCORRECT ADDRESS USED FOR ARRAY
INCORRECT ADDRESS WHEN INITIALIZING A POINTER
INCORRECT MOV INSTRUCTIONS GENERATED
INCORRECT ON-CHIP XRAM FOR ST UPSD DEVICES
INCORRECT OPERATION OF PRINTF AND SIZEOF
INCORRECT VALUE STORED IN CHAR
INCORRECT VALUES DISPLAYED FOR LOCALS
INCREASING THE SPEED OF DATA OVERLAYING
INCREMENTING A CAST POINTER PRODUCES AN INTERNAL ERROR
INCREMENTING HUGE POINTER ONLY CHANGES LOWER 16-BITS
INDENTIFY UNCALLED LIBRARY ROUTINES
INDIRECT FUNCTION CALL SYNTAX
INDIRECT FUNCTION CALLS
INDIRECT FUNCTION CALLS WITH CODE BANKING
INDIRECTLY ACCESSING 8051 SFRS
INDIRECTLY ACCESSING SFRS
INDIRECTLY CALLED REENTRANT FUNCTIONS
INFINEON C517A A/D EXAMPLE PROGRAM
INFINEON C868 EXAMPLE DOES NOT CONNECT
INFINEON C868 STARTER KIT EVALUATION BOARD
INFINEON GENERAL DSP LIBRARIES
INFINEON WATCHDOG TIMER RESETS SIMULATOR
INFINEON XC16X CAN CONTROLLER FAILS
INFINEON XC800 MDU SUPPORT
INFINEON XC866 CRASHES WHEN REGISTER BANK CHANGES
INFORMATION ABOUT MOTOR CONTROL
INI FILE DOES NOT WORK PROPERLY
INITIAL STATE OF SEMAPHORES
INITIALIZE MEMORY AT SIMULATOR START
INITIALIZING & LOCATING A VARIABLE TO A FIXED ADDRESS
INITIALIZING AN ABSOLUTELY LOCATED VARIABLE
INITIALIZING FAR DATA
INITIALIZING THE 320/520 2ND SERIAL PORT
INITIALIZING UNION MEMBERS
INITIALIZING XDATA MEMORY
INITIALIZING XDATA OVER FF00H
INITIATING A RESET
INIT_MEMPOOL FOR HEAP SETUP DOES NOT EXIST
INIT_MEMPOOL REQUIRES MORE MEMORY THAN IS ACTUALLY USED
INLINE ASSEMBLY
INLINE ASSEMBLY
INLINE ASSEMBLY GENERATES TARGET OUT OF RANGE
INLINE EXPANSION OF LIBRARY FUNCTIONS
INLINE FUNCTIONS IN C
INLINE KEYWORD SUPPORT
INLINE MACRO FUNCTIONS
INSERTING PAGE BREAKS
INSTALLATION PROBLEMS WITH USB SECURITY KEYS
INSTALLING EVAL WITH OTHER KEIL PRODUCTS
INSTALLING PL/M-51 WITH C51
INSTALLING RESULTS IN EVAL VERSION
INSTALLING RTX51
INSTALLING THE NORDIC RFPROBE DRIVER
INSTALLING THE PKLPC-8K
INSTALLING UVISION2 ON PC WITHOUT DISKETTE DRIVE
INSTRUCTION GENERATED BY PDATA OR XDATA VARIABLE
INSTRUCTION SET MANUAL
INTEGER PROMOTION
INTEL HEX FILE FORMAT
INTEL HEX FILE IS INCOMPLETE
INTEL OMF-51 OBJECT MODULE SPECIFICATION
INTEL USB HUB EXAMPLE CODE TOO SMALL
INTERFACE FOR IAP FUNCTIONS ON PHILIPS DEVICES
INTERNAL ERROR OCCURRED READING RETVAL FILE
INTERRUPT BEHAVIOUR ON INFINEON XC16X DEVICES
INTERRUPT CODE NOT IN CORRECT SPACE
INTERRUPT DEFINITION WITH ATMEL LIBRARY
INTERRUPT FOR TIMER2 LOSES SERIAL INTERRUPT
INTERRUPT GENERATES WARNING 16 (UNCALLED SEGMENT)
INTERRUPT HAPPENS MANY TIMES
INTERRUPT LATENCY WITH SILABS DEVICES
INTERRUPT LOCK OUT TIME
INTERRUPT NUMBER ALREADY USED LINKER ERROR
INTERRUPT PIPELINE QUESTIONS
INTERRUPT SERVICE ROUTINES
INTERRUPT SERVICE ROUTINES LOCATED AT WRONG ADDRESSES
INTERRUPT VECTOR NUMBERS
INTERRUPT VECTOR REDIRECTION
INTERRUPT-DRIVEN SERIAL I/O
INTERRUPTS AND LOCAL VARIABLES
INTERRUPTS DIALOG
INTERRUPTS DO NOT WORK
INTERRUPTS NOT GENERATED
INTERRUPTS ON STR9
INTERRUPTS STOP WORKING
INTERRUPTS STOP WORKING
INTERVAL DIRECTIVE
INTERVAL DIRECTIVE
INTPROMOTE/NOINTPROMOTE DIRECTIVE
INTR2 DIRECTIVE
INTVECTOR/NOINTVECTOR DIRECTIVE
INTVECTOR/NOINTVECTOR DIRECTIVE
INVALID RELOCATABLE EXPRESSION WITH CSEG/XSEG AT
INVALID SERIAL NUMBER
INVALID SERIAL NUMBER IN WEB UPDATES
INVALID SERIAL NUMBER/UNABLE TO INSTALL FROM CD
INVOKING VERSION 2 COMPILER FROM A COMMAND LINE
IPCP SUPPORT IN TCPNET PPP CLIENT
IS A DOS INTERFACE AVAILABLE?
IS CHIPVIEW RTOS AWARE?
IS ENUMERATION INFORMATION INCLUDED IN THE OMF FILE?
IS FIXDRK AN ASSEMBLER OR COMPILER DIRECTIVE?
IS INFINEON XC FAMILY SUPPORTED?
IS PK51 REQUIRED?
IS RETURN REQUIRED FOR VOID FUNCTIONS?
IS SOURCE CODE INCLUDED IN RTX OPERATING SYSTEMS?
IS STARTUP.A51 REQUIRED?
IS THE 251 SECOND SOURCED?
IS THE CLOCK SPEED 40MHZ OR 20MHZ
IS THE IEEE-695 OBJECT MODULE FORMAT SUPPORTED?
IS THE INFINEON C161CS DEVICE SUPPORTED?
IS THE KEIL ASSEMBLER A CROSS ASSEMBLER?
IS THE LINUX OPERATING SYSTEM SUPPORTED?
IS THE PHILIPS XA SUPPORTED?
IS THERE A KEIL MONITOR FOR THE INTEL USB BOARD?
IS THERE A LITTLE ENDIAN/BIG ENDIAN COMPILER OPTION?
IS THERE A TRANSLATOR FOR PL/M-51 TO C?
IS V5.1 REALLY V5.1?
ISA-ACTEL51 WON'T INSTALL WITH UVISION3
If BRESP indicates an error, does that mean that none of the transaction's data was written to memory?
If I connect DBGEN to '0' on ARM7TDMI, does this disable all debug functionality?
If I do not need all of the CCI-400 slave interfaces or master interfaces, what can I do?
If a slave receives three addresses from different masters M1, M2 and M3 in that order and has an interleaving depth of 3 can the slave expect to see any data from M3 before it sees data from masters M1 and M2?
If a slave sends an EXOKAY response after a non-exclusive transfer, when it should send an OKAY response, how does the ARM1176 behave ?
If aclk and mclk operate at same frequency, what level should a_gt_m_sync be tied to, H or L?
If aclk is synchronous to mclk in our design, should the false paths between these clock domains in pl340_dmc_compile.tcl be removed?
If multiple masters write to the same memory location, what would be the result of a following read ?
If the write buffer is full and the ARM wants to perform another write, will it stall the processor?
In AArch64 how can I read the current PC value?
In DAPML, what is the difference between DAP_READ_AP / DAP_WRITE_AP and DAP_READ_APACC / DAP_WRITE_APACC
In PL340 what is the difference between stop_mem_clk and auto_power_down?
In a system, can PL310 run at half the clock frequecy of Corxtex-A9?
In the ARM720 Technical Reference Manual chapter, it is stated that the write buffer can hold up to 8 words of data and 4 independent addresses. Why is this?
In the Timeline view of Streamline, why do the process/thread bars and detail bars not match?
In what situations might I need to insert memory barrier instructions?
In which direction do the debug scan chains scan?
In which version of RVDS was support for the Cortex-M0 added?
Installing ADT Eclipse plug-ins fails because of missing required plug-in org.eclipse.wst.sse.core
Is DS-5 available for ARMv8-A?
Is Eclipse compatible with RVDS 2.2 SP1 or earlier?
Is RTCK needed on the JTAG connection to a CoreSight DAP?
Is RTCK required as a dedicated output?
Is RVCT for BREW/BREW Builder available with a floating license?
Is RVDK for OKI available with a floating license?
Is RVDK for ST available with a floating license?
Is RVDK for XScale available with a floating license?
Is RealView Profiler supported on Windows 2000?
Is Windows Vista a supported platform for RVDS 3.1?
Is a DesignWare foundation license required to synthesize the ARM synthesizable cores?
Is a partner required to produce a Test Chip for the ARM7EJ-S?
Is an internal (I) cycle always followed by a sequential (S) cycle?
Is it OK to tie off the "HRESETn" input of an HTM?
Is it acceptable to concatenate all of the ARM720T TIF patterns to form one long file and run them all at once, with only one reset?
Is it enough for the system clock controller to only monitor csysack of PL340 to know whether PL340 has acknowledged the low power request on csysreq?
Is it legal for an AHB wrapping burst to be aligned with respect to the total number bytes in the burst, such that it does not wrap?
Is it mandatory to have ebibackoff going low at the same time as its associated ebigrant signal in PL354 using PL220?
Is it possible to configure the ARM9 core to more than 2 hardware breakpoints or watchpoints?
Is it possible to configure the cache sizes and memory timings on the RTSMs?
Is it possible to do a read-modify-write of a variable using the DAP Macro Language code supported by CoreSight Integration Kits, e.g. using DAP_READ_AP / DAP_WRITE_AP?
Is it possible to map RAM to address 0x0 on the Cortex-M3 MPS RTSM model?
Is it possible to not have arbitration if there is only one slave interface on the PL301?
Is multiplexing supported by MultiTrace?
Is semihosting supported in DS-5 for ARMv8?
Is small/medium/large equivalent to 4/8/16 bits of TRACEPKT?
Is the ARM Compiler and RVCT able to workaround the Cortex-M3 errata 602117?
Is the cache in ARM720T a write through cache or a write back one?
Is the row boundary crossing possible in case of WRAP bursts ?
Is there a C program which could build a default page table?
Is there a TAPOp equivalent for RealView ICE?
Is there a VHDL source release available for ARM7EJ-S?
Is there a priority scheme for exceptions?
Is there a restriction between aclk and mclk in asynchronous mode?
Is there a risk in using processor-only reset (SYSRESETn) rather than full reset (PORESETn) in Cortex-M3?
Is there a simple way to measure the execution performance of arbitrary code in simulation?
Is there a soft float (softfp) ABI for A64/AArch64?
Is there any memory inside PL011?
Is there any method of at-speed testing for ARM7TDMI?
Is there any requirement that Access Ports (APs) occupy consecutive positions starting from DAP Bus APSEL=0x0 (slot zero)?
Is there any way of searching in the trace window?
Is there any way of setting up trace points in the same way as setting breakpoints i.e. by using the source window?
J-LINK CAUSES RDI ERRORS AT DEBUG START
JEDEC FILE FOR THE PAL
JTAG COMMUNICATION ERROR
JTAG COMMUNICATION ERROR ON ARM
JTAG COMMUNICATION FAILURE
JTAG DEBUGGING PROBLEMS WITH XC8XX DEVICES
JTAG OCDS DEBUGGER SUPPORT
JTAG PULL-UP RESISTORS
JTAG RESET LINE FOR CORTEX-M3 DEVICES
JTAG port on MPS internal Trace Mictor connector does not work
JTAG programming problems on revision C PB926 when Logic Tiles present
JTAG signal integrity and maximum cable lengths
JUMPING TO A SECOND PROGRAM FROM A BOOT LOADER
KBHIT LIBRARY ROUTINE IS MISSING
KEEPING HEX RECORDS IN ORDER
KEIL APPLICATION NOTE 162 ERRATA FOR FX FAMILY
KEIL MON51 CONFIGURATIONS FOR EZUSB FX
KEIL USB VENDOR ID
KEIL UVISION3 SUPPORT FOR WINDOWS X64
KEIL*.SYS USB DRIVER UPDATE PROBLEM
KEIL-SPECIFIC DEVICE DRIVERS
KERNEL AWARE DEBUGGING
KEYSTROKE MACROS
Kernel debug on NVIDIA Tegra 2 platforms
Known issues with the ADS 1.2/RVCT 1.2 VFP Support Code
L104: MULTIPLE PUBLIC DECLARATION 'GETCHAR'
L138 ERROR USING OPERAND ARITHMETIC IN AN ARRAY INDEX
L210 registers always return 0x0 instead of the last value stored
L51_BANK.A51 ASSEMBLES WITH ERRORS
L6320W WARNING SWITCHING CODE TO C++
LARGE DIRECTIVE
LARGE DIRECTIVE
LATENCY OF INTERRUPT SERVICE ROUTINES
LEAVING HOLES IN CODE SPACE
LIB FILES NOT INCLUDED IN SOFTWARE UPDATES
LIBRARY PROBLEMS WITH DALLAS CONTIGUOUS MODE
LICENSE CHECK IN FROM ANOTHER WORKSTATION?
LICENSING A PC NOT CONNECTED TO THE INTERNET
LIMIT STRING OUTPUT IN PRINTF USING %S
LIMITS ON FUNCTIONS WITH VARIABLE-LENGTH ARGUMENT LISTS
LIMITS.H HEADER FILE PROBLEMS
LINE NUMBERS ARE SKEWED WHEN MACROS ARE EXPANDED
LINE NUMBERS IN A51 LISTINGS
LINK INTERBANK CALL TABLE ?BANK?SELECT
LINK PROBLEMS AFTER CHANGING COMPILER TOOLCHAIN
LINKER CODE PACKING
LINKER CODE PACKING PROBLEM
LINKER COMMAND AND RESPONSE FILES
LINKER CONFIGURATION FOR HUGE MEMORY
LINKER CONTROL FILE CAUSES LINKER ERRORS
LINKER CONTROL FILES
LINKER ERROR (UNDEFINED REFERENCE WITH C++)
LINKER ERROR L6915E WITH ATMEL EXAMPLES
LINKER ERROR WITH CORTEX-M3 DEVICE
LINKER ERRORS WHEN USING FAR MEMORY
LINKER FREEZES WHEN PERFORMING CODE PACKING
LINKER GIVES UNRESOLVED EXTERN ERROR ON OS CALLS
LINKER ISSUE AFTER UPDATE TO VERSION 4.13A
LINKER LEAVES BIG GAPS IN MEMORY WHEN USING _AT_
LINKER ORDERING SEGMENTS BY SIZE
LINKER WARNINGS AFTER UPGRADING SOFTWARE
LINKER/LOCATER ENCOUNTERED A PROBLEM
LINKING PROGRAMS FOR DS80C400 USING START400.A51 FAILS
LINKING PROGRAMS LARGER THAN 64K
LINKING RTX166 PROJECT DOES NOT WORK
LINKING USER-MODIFIED C FUNCTIONS
LINKING V6 LIBRARIES WITH V5 PROGRAMS
LINT FROM WITHIN UVISION
LIST OF BUILT-IN DEBUGGER FUNCTIONS
LISTINCLUDE DIRECTIVE
LISTINCLUDE DIRECTIVE
LISTING FILE OVERVIEW
LITTLE-ENDIAN CAN REGISTERS, BIG-ENDIAN COMPILER
LJMP & LCALL INSTEAD OF AJMP & ACALL
LJMP INSTRUCTIONS IN INLINE ASSEMBLER CORRUPTED
LJMP SWAPS MSB/LSB IN TRISCEND E5 DRIVER
LOAD APPLICATION DOESN'T MATCH ROM ERRORS
LOAD EXISTING PROJECTS
LOADING & DEBUGGING THE ATMEL 89C51RE2
LOADING PROGRAM INTO TARGET WITHOUT USING THE MONITOR
LOCAL LABELS DON'T WORK IN MACROS
LOCAL VARIABLES NOT DISPLAYED
LOCAL VARIABLES PRESERVE VALUES BETWEEN FUNCTION CALLS
LOCATE CODE CLASS IN DIFFERENT 64KB SEGMENT
LOCATE COMMON CODE SEGMENTS
LOCATE CONSTANTS TO ABSOLUTE ADDRESSES
LOCATE CONSTANTS TO FIXED LOCATIONS
LOCATE LIBRARY FUNCTIONS
LOCATE STRUCT TO SFR SPACE
LOCATE SYNTAX ERRORS WHEN USING MACROS
LOCATE VARIABLES TO ABSOLUTE ADDRESSES
LOCATE VARIABLES TO XC16X ON-CHIP ERAM
LOCATING A CODE TABLE IN A CODE BANK
LOCATING A SEGMENT'S ENDING ADDRESS
LOCATING A TABLE OF POINTERS AT A SPECIFIC ADDRESS
LOCATING A VARIABLE IN A REGISTER
LOCATING AN ECODE SEGMENT AT A FIXED ADDRESS
LOCATING ARRAYS OF STRINGS IN ROM
LOCATING CODE IN PHILIPS MX INTERNAL CODE MEMORY
LOCATING CONSTANT (CODE) VARIABLES IN A CODE BANK
LOCATING CONSTANT (CODE) VARIABLES IN A CODE BANK
LOCATING CONSTANTS IN CODE SPACE
LOCATING DATA STRUCTURES IN XDATA IN THE ORDER DEFINED
LOCATING FUNCTION TABLES IN CODE MEMORY
LOCATING FUNCTIONS AT ASCENDING ADDRESSES
LOCATING FUNCTIONS IN CODE BANKING PROGRAMS
LOCATING GROUPS OF CODE SEGMENTS TOGETHER
LOCATING IMPROPER FIXUP INSTRUCTIONS
LOCATING INDIVIDUAL SEGMENTS WHILE USING START ADDRESS
LOCATING INITIALIZED VARIABLES AT ABSOLUTE ADDRESSES
LOCATING INTERRUPTS IN EVAL SOFTWARE
LOCATING MORE VARIABLES IN THE NEAR MEMORY AREA
LOCATING MULTIPLE SECTIONS WITHOUT SPECIFYING NAMES
LOCATING OBJECT FILES AT SPECIFIC STARTING ADDRESSES
LOCATING POINTERS IN ROM
LOCATING PROGRAM OR VARIABLES TO SPECIAL AREAS
LOCATING PROGRAM SECTIONS IN ORDER
LOCATING PROGRAM SECTIONS TO SPECIAL MEMORY AREAS
LOCATING STARTUP ROUTINES IN ECODE
LOCATING THE STACK AFTER IDATA VARIABLES
LOCATING VARIABLES AT ABSOLUTE MEMORY ADDRESSES
LOCATING VARIABLES IN ASSEMBLY
LOCATING VARIABLES IN ASSEMBLY
LOCATING VARIABLES IN EDATA
LOCATING VARIABLES IN MULTIPLE XDATA AREAS
LOCATING VARIABLES TO FAR CONST SPACE
LOCATING VARIABLES TO FIXED ADDRESSES
LOCATION AND ORDER OF CONSTANTS
LOCK-UP AFTER INSTALLING UPDATE
LOCK-UP WHEN STARTED
LOG AND POW FUNCTION PROBLEMS
LOGGING A TRACE RECORDING TO A FILE
LOGGING CONTENTS OF THE DISASSEMBLY WINDOW
LOGGING MEMORY CONTENTS TO A FILE
LOGGING SERIAL WINDOW OUTPUT IN A FILE
LOGIC ANALYZER CAN'T SEE VTREGS ON ADUC836
LOGIC ANALYZER DOES NOT SHOW VARIABLE UPDATE
LOGICAL NOT ('~') GIVES INCORRECT RESULTS
LONG COMMAND LINES
LONG FILE NAMES
LONG POINTER ARITHMETIC
LONG UNSIGNED GENERATES SYNTAX ERROR
LOOKUP TABLES IN ASSEMBLY
LPC DEVICE NOT FOUND
LPC PORT TESTING PROBLEMS
LPC PWM FREQUENCY
LPC18xx/43xx On-chip Flash Loader Vector Checksum Calculation
LPC2000 APPLICATION DOES NOT REACH MAIN
LPC2000 FAST GPIO SHOW WRONG VALUES
LPC2000 FAST GPIO SHOW WRONG VALUES
LPC2000 FAST GPIO SHOW WRONG VALUES
LPC2000 FLASH UTILITY
LPC2000 SINGLE STEP AT RESET APPEARS TO FAIL
LPC2130 TIMER 1 DOESN'T RUN
LPC213X UART REPORTS OVERRUN
LPC2148 DEVICE RETURNS LPC2138 DEVICE ID
LPC9102 FLASH CANNOT BE PROGRAMMED
LPT DONGLE ON USB PORT REPLICATOR
LROL AND LROR FUNCTIONS ARE NOT INTRINSIC
LUMINARY BOARD: NO ALGORITHM FOUND
LUMINARY ON-BOARD USB DEBUGGER FAILS
Library is not created
License checkouts might slow down due to searching for IBFS32.DLL
Licensing Problem Diagnostic Scripts
Linker Error: L6242E: Cannot link object <objname> as its attributes are incompatible with the image attributes.
Linker error "Invalid relocation ... Type nn is reserved for ARM LINUX"
Linker error L6218E: Undefined symbol main (referred from kernel.o).
Loading an application using the rm_uHAL.axf image
Locating code and data in memory (Scatterloading)
Low Power RTX Applications on Cortex-M Devices
MAC UNIT SUPPORT
MACRO ASSEMBLY CODE PROBLEMS
MACRO NAMES ARE NOT EXPANDED
MACROS ARE NOT EXPANDED
MAKING BINARY FILES FROM HEX FILES
MAKING HEX FILES FROM BINARY FILES
MAKING MALLOC AND FREE REENTRANT
MAKING YOUR OWN LIBRARY FILES
MALFUNCTION WITH 6V POWER SUPPLY
MALLOC ALWAYS RETURNS NULL
MALLOC AND MEMORY ALLOCATION ROUTINES
MANUAL DOESN'T MATCH UVISION V2 SCREEN
MANUAL SAMPLE
MANUAL SAMPLE
MATH FUNCTIONS
MATH OPERATIONS SUPPORTED
MAXARGS DIRECTIVE
MAXARGS DIRECTIVE
MAXIMIZE SIMULATION SPEED
MAXIMUM LIBRARY SIZE
MAXIMUM NUMBER OF TASKS
MCB2368 RUNS INTERMITTENTLY
MDK 3.02 FOR EDUCATIONAL USE WITH ARM EVAL7T BOARD
MDK4.54: Missing new Segger emWin LCD driver
MEASURE EXAMPLE PROBLEMS IN EVALUATION SOFTWARE
MEASURING EXECUTION TIME
MEASURING TIME BETWEEN INTERRUPTS
MEMORY ADDRESS MISMATCH AT ADDRESS 0X20
MEMORY ALLOCATION
MEMORY CLASSES FOR STRINGS AND STRING POINTERS
MEMORY DISPLAY WRONG DURING FLASH PROGRAMMING
MEMORY MISMATCH AT DEBUGGER START
MEMORY MISMATCH DURING TARGET DEBUGGING
MEMORY MISMATCH ERRORS DURING LOAD
MEMORY RANGE OUT OF BOUNDS
MEMORY SETTINGS AND CLASSES RELATIONSHIP
MEMORY SPACE OVERLAP USING MON166 AND NMI
MEMORY SPACE OVERLAP WITH AT91SAM7 EXAMPLE
MEMORY TYPES FOR THE DALLAS 390 CONTIGUOUS MODE
MEMORY VERIFICATION IN BACKGROUND
MEMORY WINDOW ADDRESSES
MENTOR E8051EW SIMULATOR OPTIONS
MERGING DUPLICATE CONSTANT STRINGS
MERGING TWO APPLICATIONS INTO ONE INTEL HEX FILE
MISPLACED FCODE SECTIONS WHEN USING XLARGE MODEL
MISSING CONTENT IN HEX FILE
MISSING PARTS (J2,R7,R8) ON THE BOARD
MISSING PARTS (Q1,C8,C9) ON THE BAORD
MISSING SYMBOL 'RTX_WORKSPACEPATTERN'
MISSING TYPE-SPECIFIER DOES NOT GENERATE ERROR
MISSING UART SFR DEFINITIONS FOR PHILIPS 8XC51MX
MIXING C AND ASSEMBLY
MIXING MEMORY MODELS
MIXING MEMORY MODELS AND MEMORY AREAS
MIXING MPL MACROS AND STANDARD MACROS
MIXING NCODE AND FCODE
MIXING REENTRANT FUNCTIONS AND NON-REENTRANT FUNCTIONS
MIXING SRAM AND NVRAM
MOD517/ NOMOD517 DIRECTIVE
MODBIN DIRECTIVE
MODDP2/NOMODDP2 DIRECTIVE
MODIFY IRQ FLAG TO DISABLE/ENABLE INTERRUPTS
MODIFYING A STRUCT USING POINTERS
MODIFYING CONSTANT STRUCTURES
MODIFYING FOR WORD READS AND WRITES
MODIFYING MEMORY WHILE USING THE MONITOR
MODIFYING THE 10-PIN TO 20-PIN CABLE
MODIFYING THE STARTUP ROUTINES
MODULAR PROGRAMMING
MON51 CONFIGURED FOR I2C COMMUNICATION
MON51.DLL FOR C51 V6.00
MONITOR CONFIGURATION DOES NOT WORK IN V4.22
MONITOR DATA AREA
MONITOR EXECUTION SPEED
MONITOR FOR THE PHYTEC PHYCORE 591
MONITOR OVERHEAD
MONITOR STOPS WORKING AFTER EXECUTING CODE
MONITOR WARNING, CODE_START IS EQUAL TO VECTAB
MON_BANK CONFIGURATION FILE IS MISSING
MORE INFORMATION ABOUT SPI
MOUSE CLICK SELECTS WRONG TEXT
MOUSE OVER ARRAY NAME CAUSES CRASH
MOV #CONSTANT GENERATES C197 ERROR MESSAGE
MOVING A LICENSE TO A NEW WORKSTATION
MOVING CARRY BIT INTO ACCUMULATOR
MOVING CODE FROM FLASH TO RAM FOR EXECUTION
MOVING THE STACK
MOVING TOOLS TO A DIFFERENT FOLDER
MOVX CALLED AFTER WR_CODE RETURNS
MS VISUAL SOURCE SAFE DOES NOT WORK
MULTIPLE COMPUTERS ON A SINGLE-USER LICENSE
MULTIPLE LARGE OBJECTS IN HDATA
MULTIPLE PROGRAMS FROM 1 SOURCE FILE SET
MULTIPLE PROJECTS WITH DIFFERENT RTX LIBRARIES
MULTIPLE PUBLIC DEFINITIONS OF ?B_CURRENTBANK
MULTIPLE PUBLIC DEFINITIONS RTX_RAMTOP (PART 1)
MULTIPLE PUBLIC DEFINITIONS RTX_RAMTOP (PART 2)
MULTIPLE VARIABLES AT THE SAME ADDRESS
MULTIPLE VECTORS FOR A SINGLE INTERRUPT FUNCTION
MULTIPLICATION BUG
MULTIPLYING TWO INTS GIVES INCORRECT RESULT
MUST ABSOLUTE ASSEMBLER FILES BE LINKED?
MUTEX BEHAVIOR
MY TIMER DOESN'T WORK AS EXPECTED
Mali-55 seems to have a fully AMBA 3.0 APB compliant interface. How can I connect Mali-55 to a APB 2.0 system?
Maximum size of arrays for C/C++ compilers
Memory Issues when porting the IK test
Merging binary images together
Migrating to STM32F10xxx Std. Libraries
Missing DS-5 Linux dependencies
Missing Multiple DPTR support for some ATMEL Devices
Model Debugger and model_shell become unstable when loading large files through scripts
Multi-ICE 2.0/2.1 requires parallel port driver V1.8 or greater
Multi-ICE Server displays 'UNKNOWN' in the TAP controller box with autodetection
Multi-ICE Server fails to autodetect the chip
Multi-ICE Server reports "Could not find the Multi-ICE hardware"
Multi-ICE Server shuts itself down (on e.g. laptops) with no network
Multi-ICE cannot auto-configure my target. Can I still debug it?
Multi-ICE cannot connect to a core with a slow clock / Multi-ICE cannot connect to an AT91 board / Can I stop the core clock when debugging with Multi-ICE?
Multi-ICE interface levels and pull-up/pull-down resistors on the JTAG signals
Multi-ICE power supply issues with RVXDK
My 64 bit DSM does not work ?
My Cortex-A8 DSM does not produce a tarmac log
My IM-LT1 has solder bridges on some IC pads - Is this a manufacturing fault?
My application is not receiving notifications, what to do?
My board has a 14-pin JTAG connector. Can I use Multi-ICE or RealView ICE with it?
My code behaves strangely at higher optimization levels
My old account no longer lets me download ARM Architecture Reference Manuals
My program crashes or exits before reaching main()
My test for memory Bus Fault gets stuck repeating the fault again and again
NAME DIRECTIVE
NAMING ABSOLUTE SEGMENTS
NAMING ABSOLUTE SEGMENTS
NAMING CONVENTIONS FOR FUNCTION SYMBOLS
NESTING INTERRUPTS
NESTING INTERRUPTS
NEWSGROUPS
NO ALGORITHM FOUND FOR ADDRESS
NO BROWSE INFORMATION AVAILABLE
NO DHCP ADDRESS FROM WINDOWS 2003 SERVER
NO ERROR MESSAGES DISPLAYED IN OUTPUT WINDOW
NO I2C DIALOG IN SIMULATOR
NO ISPI FLAG WHILE WORKING WITH SPI
NO OUTPUT WHEN RUNNING PC-LINT
NO SIMULATION OF A/D CONVERTER
NOAJMP DIRECTIVE
NOALIAS DIRECTIVE
NOAMAKE DIRECTIVE
NOAMAKE DIRECTIVE
NOCASE DIRECTIVE
NOEXTEND DIRECTIVE
NOEXTEND DIRECTIVE
NOEXTEND DOES NOT WORK PROPERLY
NOFRAME DIRECTIVE
NOINDIRECTCALL DIRECTIVE
NOJMPTAB DIRECTIVE
NON-REENTRANT PRINTF
NOREGPARMS DOES NOT WORK ON REENTRANT FUNCTIONS
NORTON SEES UVISION AS "SUSPICIOUS"?
NOSORTSIZE DIRECTIVE
NOSYMBOLS DIRECTIVE AFFECTS OBJECT FILE
NOT ALL CODE BANK HEX FILES ARE GENERATED
NOT ALL GLOBAL VARIABLES ARE INITIALIZED
NOT ALL INTERRUPT SOURCES APPEAR IN DIALOG
NOT FINDING SOME FUNCTIONS IN LIBRARIES
NULL POINTER COMPARE FAILS WHEN MIXING MEMORY TYPES
NULL POINTER COMPARE FAILS WITH MALLOC AND CALLOC
NUMBER OF ACTIVE USERS ON A FLOATING LICENSE
No Trace Synchronization on Freescale K70 Board
Node Emulator displays 'timeout' messages while registration update
Node Emulator fails to connect to the Device Server when started in TCP mode
Non-stop Semihosting or the Channel Viewer or the Debug Comms Channel doesn't work
OBJECT FILE FORMATS GENERATED
OBJECT/NOOBJECT DIRECTIVE
OBJECT/NOOBJECT DIRECTIVE
OBJECTEXTEND DIRECTIVE
OBTAINING AN INCLUDE FILE FOR A PARTICULAR DEVICE
OBTAINING THE MEMORY MAP OF A PROJECT
OBTAINING THE PARITY OF A CHARACTER
OBTAINING THE PARITY OF A CHARACTER
OBTAINING THE SEGMENT OFFSET OF AN SFR
OC51 FAILED TO CREATE HEX FILE
OCDS DEBUGGER LPT WIGGLER PROBLEMS
OCDS DEBUGGER WITH USER APPLICATION IN ROM
OCDS: PROGRAM COUNTER MOVES TO INCORRECT VALUES
OFFSETS WITH FAR MEMORY ACCESS
OLD BLINKY IRQ EXAMPLE DOES NOT WORK
OLD COMPILATION TOOLS IN MDK-ARM VERSION 4.13A
OLD DLL VERSION INCOMPATIBLE
OLED Display on TI LM3S8962 Board
OMF166 FILE FORMAT
ON-CHIP BANKED PDATA SUPPORT
ON-CHIP MEMORY CONFIGURATION FOR STM UPSD DEVICES
ON-CHIP ROM OPTION
ON-CHIP XRAM OPTION IS UNAVAILABLE
ON-CHIP XRAM SIZE ISSUE OVER THE ADUC832 /
ONE-SHOT SIGNAL FUNCTIONS
ONLY UPPER BYTE IS TRANSFEERED DURING PEC
OPENS WRONG HEADER FILE
OPERATING SYSTEM INITIALIZATION
OPTIMIZE DIRECTIVE
OPTIMIZE(7) DIRECTIVE
OPTIMIZED C WITH INLINE ASSEMBLER
OPTIMIZER LEVELS AND VOLATILE VARIABLES
OPTIMIZING VARIABLE MEMORY TYPES
OPTIMUM ACCESS TO ASIC SFR PAGE
OPTIMUM CODE FOR BIT TO BYTE CONVERSION
OPTIONS FOR CREATING HUGE PROGRAMS
ORDER DIRECTIVE
ORDER DIRECTIVE
ORDER OF BITFIELDS
ORDER OF FILES IN A PROJECT
ORDER OF MODULES IN LINKING USING IN-LINE ASSEMBLY
ORDER OF TASKS WAITING ON SEMAPHORE
ORGANIZING TASK EXECUTION
OSEK COMPATIBLE RTOS
OS_GET_BLOCK GIVES WARNING 20 (DATA TYPES DIFFERENT)
OS_SEND_SIGNAL FLAG
OS_WAIT DOESN'T DELAY FOR SPECIFIED TIME
OUT OF MEMORY ERROR MESSAGE
OUT OF STACK SPACE
OUTPUT CODE COVERAGE DETAILS
OVERLAY DATA FROM INTERRUPT ROUTINE WITH MAIN
OVERLAYABLE SEGMENTS AND MEMORY MODELS
OVERLAYING BIT-ADDRESSABLE SEGMENTS
OVERLAYING DATA WITH ORG EMITS NO WARNINGS
OVERWRITE ABORT HANDLER FUNCTIONS
Older CM1136JF-S boards will not boot with FPGA image 'RevD build7'
On what platforms are the Fast Models (System Generator) supported?
On what platforms will my ARM development tools work?
On what virtual platforms will my ARM development tools work?
Optimising license checkouts from a floating license server
Out of memory error
PACK DIRECTIVE
PACK DIRECTIVE
PACKETS LOST ON TCP/IP STACK
PACKING BYTES IN UNIONS AND STRUCTURES
PAG AND POF FROM POINTERS
PAGE OVERRIDE OPERATOR GENERATING INCORRECT ADDRESS
PAGELENGTH DIRECTIVE
PAGELENGTH DIRECTIVE
PAGEWIDTH AND PAGELENGTH PARAMETER INVALID
PAGEWIDTH DIRECTIVE
PAGEWIDTH DIRECTIVE
PAL EQUATION UPDATE FOR 8051 DEVICES
PARM51/PARM251 DIRECTIVE
PARTS OF SOURCE FILE ARE NOT DISPLAYED
PASSING DEFINITIONS IN THE COMPILER INVOCATION LINE
PASSING PARAMETERS TO INDIRECTLY CALLED FUNCTIONS
PB.8 + PB.9 LED PROBLEM
PB1176 DIP switches - User Guide does not match the behaviour of my board
PC incorrect after hitting a watchpoint
PC-LINT AND _AT_ KEYWORD
PC-LINT FOR 251
PC-LINT INSTALLATION
PDATA AND DALLAS DS5002
PDATA AND PHILIPS 89C668
PEC REGISTERS DO NOT WORK IN THE DEBUGGER
PERFORMANCE ANALYZER DATA ISN'T CORRECT
PERFORMANCE ANALYZER DISPLAYS HIGH VALUES
PERFORMANCE ANALYZER DOES NOT SHOW TIMES
PERFORMANCE ANALYZER UNITS
PERFORMING A SOFTWARE RESET
PERFORMING A SOFTWARE RESET IN C
PERIODIC WINDOW UPDATE DOES NOT WORK
PERIPHERAL REGISTER ACCESS CALLS DABT_HANDLER
PERIPHERALS MENU DOES NOT MATCH DEVICE
PFQBC (PREFETCH QUEUE) ENABLE IN STR91X.S
PHILIPS 87C51RC 512-BYTE INTERNAL RAM SUPPORT
PHILIPS 89C51
PHILIPS LPC SUPPORT
PHILIPS LPC2000 ARM DEVICE DOES NOT REACT
PHILIPS MX ROM (HUGE) LINKS WRONG LIBRARIES
PHILIPS MX STARTUP MODIFICATION GENERATES STRANGE CODE
PHILIPS P8XC557E8 2KB INTERNAL RAM SUPPORT
PHILIPS SMARTMX DBOX SUPPORT
PHYSICAL LOCATION OF REGISTERS
PL180 TRM link from Google is broken
PL330 scatter-gather implementation without manager thread
PL340 burst termination
PL340 has a new cclken signal as part of its AXI C interface. What does this signal do?
PL340: *Denali* Error: Bank 0 must be in the active state before accepting command 'Read'.
PLACING CODE AT A FIXED ADDRESS
PLACING FAR VARIABLES AT ABSOLUTE LOCATIONS
PLACING VARIABLES IN NON-VOLATILE RAM
PLAIN CHAR VS. SIGNED CHAR
PMU counters are reading zeroes in Streamline
POINTER ALIAS PROBLEMS
POINTER ARITHMETIC DELIVERS UNEXPECTED RESULTS
POINTER ASSIGNMENT CRASHES IN THE CONTIGUOUS MODE
POINTER STORAGE SIZE
POINTER TRUNCATION FOR IDENTICALLY DECLARED POINTERS
POINTER WATCH PROBLEM IN DEBUGGER
POP INTRINSIC GENERATES UNRESOLVED EXTERNAL
PORT 1 ERROR MESSAGE BOX
PORT LEDS DO NOT DISPLAY AS EXPECTED
PORT LINES DON'T TOGGLE DURING MEMORY ACCE
PORT PINS P1.2 AND P1.3 CANNOT BE RECONFIGURED
PORT2 LEDS DO NOT WORK
PORTING CODE FROM PL/M-51
PORTING FROM OLDER TO NEWER TOOLS
PORTING IAR XMEM TO KEIL XDATA
POST INCREMENT ON LONG FAR TYPES
POW FUNCTION PRECISION PROBLEMS
POWER PROBLEMS WITH 6 VOLT POWER SUPPLY
POWER SUPPLY PROBLEM ON MCB900 V4
POWER-UP SEQUENCE
PRE-DEFINED MACROS
PRE-FETCH ABORT
PRECISION OF PRINTF %F FORMAT STRING
PREDEFINED MACROS
PREEMPTION AND MAILBOXES
PREMATURE END OF FILE ERROR
PREPRINT DIRECTIVE
PREPRINT DIRECTIVE
PREPRINTONLY DIRECTIVE
PREPRINTONLY DIRECTIVE
PRESSING INT1 CAUSES A RESET
PREVENTING COMMON BLOCK OPTIMIZATION
PRINT/NOPRINT DIRECTIVE
PRINT/NOPRINT DIRECTIVE
PRINTF DOES NOT PRINT THE LAST CHARACTER
PRINTF EXPANDS '0X0A' INTO '0X0A'+'0X0D'
PRINTF GIVES WRONG VALUES
PRINTF LIBRARY ROUTINE PROBLEM WITH 0-LENGTH PRECISION
PRINTF OUTPUT TO MULTIPLE DEVICES
PRINTF OUTPUTS 0.000000 FOR FLOAT VARIABLES
PRINTING IN COLOR
PRINTING SUPPORT SOLUTIONS KNOWLEDGEBASE ARTICLES
PRINTING THE CONTENTS OF THE BUILD WINDOW
PROBLEM WITH INITIALIZED VARIABLES ON ADUC7000
PROBLEMS ACCESSING STRUCTURES USING POINTERS
PROBLEMS CREATING HEX FILES FOR BANKED PROJECTS
PROBLEMS IMPORTING DAVE FILES
PROBLEMS IN SCANF AND SSCANF
PROBLEMS INITIALIZING ABSOLUTELY LOCATED VARIABLES
PROBLEMS INITIALIZING BITFIELD WITH POINTER
PROBLEMS ON C16X DUE TO PIPELINE EFFECTS
PROBLEMS OPENING HEADER FILES WITH CODEWRIGHT
PROBLEMS SEARCHING THE KEIL WEB SITE
PROBLEMS SIMULATING THE SERIAL INTERFACE
PROBLEMS SOLVED IN C166 V4.11
PROBLEMS SOLVED IN C251 V2.14
PROBLEMS SOLVED IN C251 V3.20
PROBLEMS SOLVED IN C51 V5.50
PROBLEMS SOLVED IN C51 V6.01
PROBLEMS SOLVED IN C51 V6.02
PROBLEMS SOLVED IN C51 V6.02 - V6.14
PROBLEMS SOLVED IN C51 V6.12
PROBLEMS SOLVED IN C51 V6.20 - V6.23
PROBLEMS SOLVED IN C51 V7.00 - V7.01
PROBLEMS TO RUN EXAMPLE USING PHYCORE390 BOARD
PROBLEMS USING '#' IN PRINTF/SPRINTF
PROBLEMS USING PRINTF
PROBLEMS WHEN CODE START IS 0X20 - 0X7FFF
PROBLEMS WHEN LOCATING FUNCTIONS IN CODE BANKS
PROBLEMS WITH #PRAGMA ASM
PROBLEMS WITH BATTERY BACKUP RAM
PROBLEMS WITH C++ SOURCE LEVEL DEBUGGING
PROBLEMS WITH CODE BANKING AND SECONDS DIS
PROBLEMS WITH CODE BANKING SUPPORT
PROBLEMS WITH DUAL DATA POINTERS AND SERIAL BREAK
PROBLEMS WITH EARLY CYGNAL SILICON
PROBLEMS WITH FUNCTION POINTERS OVERWRITING VARIABLES
PROBLEMS WITH HYPHENS IN FILENAMES AND PROJECT NAMES
PROBLEMS WITH IN-SYSTEM PROGRAMMING USING FLASHMAGIC
PROBLEMS WITH LOCAL VARIABLES IN INTERRUPTS
PROBLEMS WITH LONG COMPARISONS TO 0 IN V6.21
PROBLEMS WITH MON51 AND TIMER 2
PROBLEMS WITH PC-LINT VERSION 7.5
PROBLEMS WITH PROGRAM EXAMPLES
PROBLEMS WITH PROGRAMMING/EMULATION MODE SWITCH
PROBLEMS WITH REGISTER OPTIMIZATION IN V6.22
PROBLEMS WITH THE INFINEON EASY UTAH BOARD
PROBLEMS WITH THE USER STACK
PROBLEMS WITH THE XDATA SIZE IN TARGET OPTIONS
PROBLEMS WITH _AT_ ADDRESSES IN V2.12A
PROGRAM CRASHES WHEN LOADED BELOW 100H
PROGRAM DOES NOT REACH MAIN
PROGRAM ERROR SIMULATING C8051F330 DEVICE
PROGRAM EXECUTION CAUSES TRAPS
PROGRAM EXITS AFTER PASTING TEXT
PROGRAM FAILS AFTER ADDING CODE
PROGRAM HANGS CASTING INT TO FLOAT ON DALLAS 400
PROGRAM HANGS ON SWI INTERRUPT
PROGRAM NEVER REACHES MAIN
PROGRAM OFF-CHIP FLASH ROM ON STR71X
PROGRAM STRUCTURE FOR REGISTER OPTIMIZATION
PROGRAM WORKS DIFFERENTLY USING LICENSED VERSION
PROGRAM-WIDE SOURCE/ASSEMBLY LISTING
PROGRAM-WIDE SOURCE/ASSEMBLY LISTING
PROGRAM-WIDE SOURCE/ASSEMBLY LISTING FILE
PROGRAMMER REPORTS THIS IS NOT A LPC9XX DEVICE
PROGRAMMING ADAPTER FOR CHIPS OTHER THAN LPC93X
PROGRAMMING FLASH ON MCB21XX BOARDS
PROGRAMMING LPC DEVICES
PROGRAMMING THE CYPRESS CY3671 FOR GPIF ACCESS
PROGRAMS BUILT WITH MAKE UTILITIES
PROGRAMS THAT USE ONE REGISTERBANK
PROJECT BUILD STOPS UNEXPECTEDLY AT PL/M MODULE
PROTECTION FAULT USING LUMINARY DLL
PSW NOT UPDATED USING BMOV INSTRUCTION
PURPOSE OF 'VOLATILE' AND 'CONST' KEYWORDS
PURPOSE OF ?C?INITEDATA
PURPOSE OF INT_CLOCK
PURPOSE OF START167.A66
PURPOSE OF THE INIT.A51 FILE
PUTTING INITIALIZED VARIABLES IN XDATA
PUTTING INTERRUPTS IN FLASH ROM
PUTTING TABLES IN HCONST
Performance Monitor Unit example code for ARM11 and Cortex-A/R
Placement of small global ZI data (<= 8 bytes) in memory
Placing (constant) jump tables in ROM
Placing C variables at specific addresses to access memory-mapped peripherals
Placing root region library objects in a scatter file
Problems / corruption when accessing memory mapped peripheral registers in RVD
Problems connecting a JTAG ICE to an IM-LT3 + LT platform
Problems connecting to ADI Engineering IXP425 Coyote board
Problems with CM1136JF-S test chip internal PLL and SRAMs
Problems with sprintf, when printing doubles or long longs
Progcards_multiice and Progcards_usb cannot program LT-XC2V8000 Logic Tile
Progcards_rvi gives error message "Unable to find prog_engine_X_Y in the current directory"
Progcards_rvi will not program the PB-A8
Progcards_usb versions 2.52 and earlier cannot reprogram Logic Tile bytestreamer PLD
Question regarding address translation with ARM926EJ-S
Questions on PL081 TransferSize value
Quick-start Guide for Benchmarking
R14 CORRUPTED DURING CLOCK INTERRUPT ON AT91RM9200
RAMSIZE DIRECTIVE
RAMSIZE FOR THE PHILIPS 87C528
RAMSIZE PARAMETER OUT OF RANGE (FOR PHILIPS 89C66X)
RANDOM SYSTEM CRASHES
RATE MONOTONIC SCHEDULING
RE-LICENSING ISSUES
RE-USE LIBRARY FUNCTIONS FROM A BOOT APPLICATION
RE-USING INLINE FUNCTIONS
READ-MODIFY-WRITE REGISTERS
READING CODE SPACE
READING FROM AN INPUT PORT
READING PORT INPUT VERSUS PORT LATCH
READING THE PROGRAM COUNTER
REAL-TIME AGENT
REALVIEW COMPILER OPTIONS
REALVIEW COMPILER OUTPUT FORMATS
RECOVER ACCESS TO FLASH
RECOVER FROM CORRUPTED SCREEN LAYOUT
RECOVER STR71X WHEN JTAG DISABLE
RECOVER STR75X WHEN JTAG DISABLED
RECURSIONS DIRECTIVE
RED DOTS BESIDE FILES AND GROUPS IN PROJECT
REDIRECTING INTERRUPT VECTORS
REDIRECTING INTERRUPT VECTORS
REDIRECTING SERIAL I/O TO OTHER UARTS
REDUCE MEMORY FOOTPRINT OF TCP/IP STACK
REENTRANCY ISSUES WITH THE DALLAS 390 MATH ACCELERATOR
REENTRANT AND THREAD-SAFE LIBRARY FUNCTIONS
REENTRANT FUNCTIONS
REENTRANT FUNCTIONS AND THE REENTRANT STACK POINTER
REENTRANT FUNCTIONS AND VARIABLES
REENTRANT FUNCTIONS IN LARGE OR SMALL MEMORY MODELS
REENTRANT STACK NEEDED FOR REENTRANT LIBRARY FUNCTIONS?
REENTRANT TASKS
REFERENCING C FUNCTIONS FROM C++
REGFILE DIRECTIVE
REGFILE DIRECTIVE
REGISTER PRESERVATION WITH API CALLS
REGISTER USAGE OVER XBANKING.A51 FUNCTIONS
REGISTER VARIABLES
REGISTERBANK DIRECTIVE
REGPARMS/NOREGPARMS DIRECTIVE
REINSTALLING USB DRIVER
RELEASE NOTES
RELOCATE SYSTEM STACK FROM IDATA TO SDATA
RELOCATING AUTOVECTOR INTERRUPTS ON THE CYPRESS EZ-USB
RELOCATING INTERRUPT BASE ADDRESS
RELOCATING INTERRUPT VECTOR TABLES
RELOCATING INTERRUPTS
RELOCATING PROGRAM CODE IN C
RELOCATING REGISTER BANKS
RELOCATING RESET AND INTERRUPT VECTORS
REMOTE CONTROL OF IDE AND DEBUGGER
REMOVING AND DISABLING WARNING 13 (RECURSIVE CALL)
REMOVING DEBUGGING INFO FROM ONLY SOME MODULES
REMOVING FILE HISTORY
REMOVING LINKER WARNING L16 (UNCALLED SEGMENT)
RENAMECODE DIRECTIVE
RENAMING CLASSES IN A C MODULE
RENAMING MULTIPLE DATA CLASSES IN C
REPLACE AJMP/ACALL WITH LJMP/LCALL
REPLACING LIBRARY FUNCTIONS
REPLACING MEM AND STR LIBRARY ROUTINES
REPLACING SINGLE CAN MESSAGE OBJECTS
RESERVE MEMORY AT ABSOLUTE BANK ADDRESSES
RESERVING CODE SPACE
RESERVING MEMORY ACCESSED WITH XBYTE AND XWORD
RESERVING SPACE IN CODE BANKS
RESERVING SPACE IN CODE MEMORY
RESET BEHAVIOUR ON PHILIPS LPC2000 DEVICES
RESET VECTOR DOES NOT JUMP TO C CODE
RESET VECTOR JUMPS OUTSIDE STARTUP AREA
RESTORING DEFAULT COLORS AND FONTS-SETTINGS
RESTRICTED DSCOPE
RESTRICTIONS DEBUGGING ON TARGET HARDWARE
RESTRICTIONS DEBUGGING WITH A MONITOR
RESTRICTIONS USING REGISTERBANKS
RET AND RETS GENERATED IN THE SAME FUNCTION
RET IS REPLACED WITH RETI OR RETS
RET VAL FILE NOT FOUND
RETURN(0) IN A VOID FUNCTION
RET_ISTK DIRECTIVE
RET_PSTK DIRECTIVE
RET_XSTK DIRECTIVE
REVERSE COMPILER
REVERSE ORDER DW KEYWORD
REVIEW OBJECT-HEX CONVERTER INVOCATION
RISM FOR USB CRASHES AT STARTUP
RM Build Options
RMII CLOCK ON PINCORRECT
RMTarget does not re-enable IRQs correctly
ROM DIRECTIVE
ROM DIRECTIVE
ROM(COMPACT)
ROUNDING PROBLEMS WITH FLOATING-POINT NUMBERS
RT-AGENT EXAMPLE PROJECTS DO NOT BUILD
RTC 32.768KHZ XTAL NOT WORKING
RTC INTERRUPT REQUEST FLAG REMAINS SET IN SIMULATOR
RTX - CANNOT INITIALIZE REALTIME LIBRARY KERNEL
RTX KERNEL MODE USED IN ARM CPU
RTX KERNEL NOT INCLUDED
RTX KERNEL NOT INCLUDED
RTX-TINY TASKLIST IS EMPTY
RTX51 AND TRISCEND BANKING WITH CUSTOM L51_BANK.A51
RTXFULL.DLL NOT FOUND
RTXSETUP CAN'T FIND VB400016.DLL
RTX_TINY FOLDER VS RTXTINY2 FOLDER
RUNNING A BATCH FILE/EXECUTABLE FILE BEFORE BUILD
RUNNING AT 96MHZ
RUNNING AT91SAM7S64 EXAMPLE PROGRAMS
RUNNING AUTOMATED TEST SESSIONS
RUNNING CODE FROM IDATA
RUNNING EXE/COM/BAT PROGRAMS DURING BUILD
RUNNING FROM A DOS BOX
RUNNING IN EVAL AFTER INSTALL
RUNNING RISM-251 FASTER THAN 19,200 BAUD
RUNNING UNDER VISTA OR WINDOWS 7
RUNTIME DETERMINATION OF LAST XDATA ADDRESS USED
RVCT 2.2 or 3.0 compiler reports Internal Fault 0x040b for large Thumb leaf functions
RVD Scripting & Automation
RVI Target Interface levels and pull-up/pull-down resistors on the JTAG signals
Random stopping or failure to start the debugger
Reads from DWT registers return unexpected values
RealView ICE Update reports a time-out or fails to program a DSTREAM / RealView ICE correctly
RealView ICE version 1.1 Installation Problems on Solaris
RealView Installation problems on Solaris
Rear panel JTAG port does not work on MPS
Restoring the boot monitor on the Evaluator-7T board
S:, T:, U:, AND V: USER MEMORY TYPES
SAVE / RESTORE CODE COVERAGE INFORMATION
SAVE AS CAPABILITY
SAVE MEMORY CONTENTS TO A FILE
SAVE/RESTORE DIRECTIVE
SAVE/RESTORE DIRECTIVE
SAVESYS DIRECTIVE
SAVEUSR DIRECTIVE
SAVING AND LOADING MEMORY AREAS
SAVING AND RESTORING THE PROGRAM COUNTER
SAVING AND RESTORING XDATA BANKING INFORMATION
SAVING EXTRA VARIABLES ON THE STACK
SAVING REGISTERS IN INTERRUPTS
SAVING RETURN ADDRESSES ON USER STACK
SBIT MODIFICATIONS NOT CORRECTLY WRITTEN TO MEMORY
SCANF %F FAILS WITH USER-DEFINED GETKEY FUNCTION
SCANF() BEHAVES INCORRECTLY
SCOPE OF #DEFINE
SCREEN ARTIFACTS WITH TAB CHARACTERS
SCRIPT TO OUTPUT CIRCULAR BUFFER
SECOND SERIAL PORT ON THE ST UPSD32XX
SECTOR ZERO ERASE FAILED
SEEING CLEARCASE DIRECTORIES
SELECTING BRIEF 3.1 EMULATION
SELECTING C251 V1 AND V2 TOOLS
SELECTING DIFFERENT GNU VERSIONS
SELECTING DIFFERENT REGISTER BANKS IN A FUNCTION
SERIAL CABLE WIRING
SERIAL EXAMPLE IN GETTING STARTED BOOK FAILS
SERIAL INTERRUPT OF MONITOR DOES NOT WORK
SERIAL ISR OVERWRITTEN WHEN USING NMI ONLY OPTION
SERIAL LOOPBACK SCRIPT
SERIAL PORT EXAMPLES IN MANUAL DO NOT WORK
SERIAL PORT VTREGS FOR SILABS F12X/F13X SIMULATION
SERIAL WINDOW CHARS ABOVE 0X7F
SERIAL WINDOW UNDER TRISCEND AND CYGNAL
SERIAL0 CANT BE USED FOR MON390 ON DALLAS TINI M400
SERVICE INSTALLATION SECTION IN INF FILE INVALID
SETTING A DEFAULT DIRECTORY FOR FILES
SETTING A WATCHPOINT ON A MEMORY LOCATION
SETTING BREAKPOINTS ON IDATA MEMORY
SETTING CONFIGURATION BYTES FOR THE C164
SETTING FILES EXTENSIONS
SETTING MARGIN FOR PRINTER
SETTING OR CLEARING BITS IN THE ACCUMULATOR
SETTING PROGRAM START ADDRESS
SETTING ROUND-ROBIN TIMESHARING TO 1
SETTING THE ADDRESS OF CONFIG BYTES
SETTING THE DEVICE CONFIGURATION BYTES
SETTING THE LOCATION OF THE REENTRANT STACK POINTER
SETTING THE SIZE OF CODE SPACE
SETTING UP THE PL/M-51 COMPILER
SETTING XDATA MEMORY LIMIT FOR C51 PROGRAMS
SETUP DOES NOT WORK ON WINDOWS NT4
SETUP PROJECTS WITH RTX KERNEL
SFRS LISTED FOR EACH SOURCE FILE
SHARE INTERRUPT VECTOR WITH BOOT LOADER
SHARING SERIAL PORT WITH USER APPLICATION
SIDE-EFFECTS OF VPRINTF AND VSPRINTF
SIGNED BIT FIELD NOT SUPPORTED
SIGNUM 8051 EMULATOR SYMBOL CONVERTER
SILABS USB DEBUG ADAPTER DOES NOT WORK IN UVISION3
SILABS USB DEBUG ADAPTER DOES NOT WORK IN UVISION4
SILABS µVISION2 DRIVER CRASHES ON LOAD
SIMULATE UCFGX REGISTERS FOR PHILIPS LPC9X
SIMULATING AN OUTPUT CONNECTED TO AN INPUT
SIMULATING ASC1 OF INFINEON XC16X DEVICES
SIMULATING CAN ON THE C167C DEVICES
SIMULATING INT0 INTERRUPT
SIMULATING ON-CHIP EEPROM
SIMULATING PDATA MEMORY
SIMULATING REMAP ON ATMEL AT91 DEVICES
SIMULATING RESET OF INFINEON XC16X DEVICES
SIMULATING RP0H ON THE C167
SIMULATING UNSUPPORTED INTERRUPTS
SIMULATING XC16X INTERRUPT VECTORS AT 0XC00000
SIMULATION CANNOT BE STOPPED ON TOSHIBA LAPTOP
SIMULATION OF I2C MEMORY DEVICE
SIMULATION OF THE X2 CLOCK MODE ON PHILIPS DEVICES
SIMULATION ON SILABS DEVICE NOT CYCLE ACCURATE
SIMULATION SUPPORT
SIMULATION TIMING OF SIGNAL FUNCTIONS
SINE WAVE SIGNAL FUNCTION
SINGLE QUOTE (`) IN FRONT OF WATCH VARIABLES
SINGLE STEP WITH ULINK JUMPS TO ADDRESS 20H
SINGLE STEPPING ON LJMP INSTRUCTION AT 18MHZ
SINGLE-STEP AND TRACE
SKIPPING UNUSED ADDRESS RANGE
SLOG FAILS SIMULATING 51MX DEVICES
SLOW DOWNLOAD AND DEBUGGING PROCESS USING CYGNAL UC
SLOW MENU AND WINDOW UPDATE
SMALL DIRECTIVE
SMALL DIRECTIVE
SMALL PROGRAM DOES NOT FIT INTO MEMORY
SMC USB CHIPS
SOFTWARE RESET IN C
SOFTWARE RESET USING THE MONITOR
SOME HLP FILES DON'T WORK UNDER WINDOWS
SOME PINS DO NOT PROVIDE HIGH VOLTAGE
SORTING INTEL HEX FILES
SOURCE BROWSER AND EC++
SOURCE BROWSER PROBLEMS IN ASSEMBLER KIT
SOURCE BROWSER PROBLEMS WITH OBJECT DIRECTORY
SOURCE CODE DOESN'T DISPLAY IN MY EMULATOR
SOURCE CODE SYNCHRONIZATION PROBLEMS
SOURCE LEVEL DEBUG DOES NOT WORK IN FLASH
SOURCE LEVEL DEBUGGING OF LIBRARY CODE
SOURCE LEVEL DEBUGGING WITH GNU ARM
SOURCE LINE AFTER A COMMENT IS IGNORED
SOURCE/SYMBOLS IN EMULATOR SOFTWARE
SPACES INSERTED INSTEAD OF TABS
SPECIFYING CODE AND XDATA RANGES
SPECIFYING CODE BANKS FOR BANK SWITCHING
SPECIFYING HEADER PATHS FROM THE COMMAND LINE
SPECIFYING LOWERCASE SECTION NAMES
SPECIFYING ORDER OF FILES IN PROJECT
SPECIFYING THE DIRECTORY FOR OBJ FILES
SPECIFYING THE ORDER IN WHICH OBJ FILES ARE LINKED
SPECIFYING USER LIB DIRECTORIES
SPECIFYING WHICH REGISTER BANKS ARE USED
SPEEDOVL DIRECTIVE
SPLITTING CODE BETWEEN EPROM AND FLASH MEMORY
SPLITTING CODE BETWEEN EPROM AND FLASH/EEPROM
SPLITTING HEX FILES
SPORADIC INTERRUPT PROBLEMS
SPRINTF AND FAR STRINGS
SPRINTF CONVERTS FLOAT VARIABLES TO ZERO?
SRC DIRECTIVE
SRC DIRECTIVE
SRC DIRECTIVE
SROM MACROS RETURN INCORRECT ADDRESSES
SSCANF RETURNS INCORRECT NUMBER OF PARAMETERS SCANNED
SSP1 INTERFACE DOES NOT WORK
ST-LINK - NO FOUND WITH MDK VERSION 4.11
ST10-F269 BONDOUT DEVICE MAC.1 CHIP BUG WORKAROUND
STACK AND REENTRANT STACK SYMBOLIC NAMES
STACK POINTER INITIALIZATION IN STARTUP CODE
STACK REQUIREMENTS
STACK REQUIREMENTS OF RUN-TIME LIBRARY FUNCTIONS
STACK UTILIZATION
START PROBLEM ON POWER-UP
START PROBLEM WITH PHYTEC PHYCORE LPC2294
START167 AND BOOT167
START167.A66 FOR EVALUATION BOARDS
STARTING A FUNCTION AT A SPECIFIC ADDRESS
STARTING A NEW PROJECT
STARTING ADDRESS FOR VARIABLES IN RAM
STARTING AND STOPPING TRACE CAPTURE
STARTING PROGRAMS AT ADDRESSES OTHER THAN 0000H
STARTING UV2 AFTER CHANGING PROJECT PATH NAMES
STARTUP CODE CHANGES DO NOT WORK WITH MCB167-NET
STARTUP CODE CHANGES REQUIRED TO USE ECODE
STARTUP CODE UNRESOLVED EXTERNAL (?B_SWITCH0)
STARTUP DESIGNS FOR EMBEDDED PROGRAMS
STARTUP FILE
STARTUP PROBLEMS WITH INFINEON OCDS ON XC16X
STARTUP.S FILE TRANSLATES WITH MANY ERRORS
STATIC DATA VARIABLES
STATIC FUNCTION POINTERS
STATIC INTERRUPT FUNCTIONS
STATIC POINTERS VS EXPLICITLY PLACED VARIABLES
STDARG.H QUESTIONS
STDDEF.H CREATES WARNING
STM32 FLASH OPTION BYTES PROGRAMMING
STM32 FLASH OPTION BYTES PROGRAMMING FAILS
STOP PERIPHERALS ON BREAKPOINTS
STOPPING BUILD WHEN WARNINGS ARE DETECTED
STOPPING PROGRAM EXECUTION ON VARIABLE WRITE
STORAGE OF LOCAL VARIABLES
STR7 INTERRUPT HANDLERS
STR9 FLASH PROGRAMMING
STRANGE BEHAVIOR OF PROGRAM CODE
STRANGE DATA RECEIVED SHARING THE SERIAL P
STRANGE ERRORS WITH IN-LINE ASSEMBLER CODE
STRANGE PROBLEMS USING INTERRUPTS
STRANGE PROBLEMS WITH APPLICATION SOFTWARE
STRANGE SINGLE-STEPPING USING GNU IN THUMB MODE
STRING TABLE IN XDATA
STRING TABLES IN C
STRTOD LIBRARY ROUTINE
STRTOL LIBRARY ROUTINE
STRTOUL LIBRARY ROUTINE
STRUCTURE MEMORY SPACE DETAILS IN LISTING FILES
SUBKEY ERROR INSTALLING ULINKPRO
SUPPORT FOR -I AND -D MAKEFILE COMMANDS
SUPPORT FOR C505 DATA POINTERS
SUPPORT FOR DEVICES WITH UNDER 2K CODE SPACE
SUPPORT FOR FLASHMAGIC
SUPPORT FOR FLOATING-POINT NUMBERS
SUPPORT FOR INLINE KEYWORD
SUPPORT FOR INTEL 8XC52, 8XC54, 8XC58
SUPPORT FOR J-LINK
SUPPORT FOR PHILIPS P89C51RC & P89C51RC2
SUPPORT FOR PHILIPS SJA1000
SUPPORT FOR SEGGER J-LINK
SUPPORT FOR SILICON LABS DEVICES
SUPPORT FOR SST DEVICES
SUPPORT FOR THE 515C EIGHT DATA POINTERS
SUPPORT FOR THE 8744 SDLC MICROCONTROLLER
SUPPORT FOR THE 8X930AX/HX
SUPPORT FOR THE ATMEL AT89C
SUPPORT FOR THE ATMEL AVR AND AT90 DEVICES
SUPPORT FOR THE ATMEL T80C51 DEVICES
SUPPORT FOR THE CYGNAL F04X FAMILY
SUPPORT FOR THE DALLAS 390
SUPPORT FOR THE INTEL B-STEP AND C-STEP DEVICES
SUPPORT FOR THE LPC900 DEVICES
SUPPORT FOR THE PHILIPS 80C51RX
SUPPORT FOR THE PHILIPS 87C652
SUPPORT FOR THE PHILIPS 87LPC764
SUPPORT FOR THE PHILIPS P89C66X DEVICES
SUPPORT FOR THE PHILIPS XA
SUPPORT FOR THE SGS-THOMSON ST10R262 MAC
SUPPORT FOR THE SIEMENS C161CI
SUPPORT FOR THE SIEMENS DECT472X
SUPPORT FOR THE SST89C5X
SUPPORT FOR THE SST89C5X
SUPPORT FOR THE ST10F168
SUPPORT FOR THE WINBOND W77C32
SUPPORT IN FULL 8051 TOOLS
SUPPORT OF NON-STANDARD CHIP FEATURES
SUPPORTED DATA TYPES
SUPPRESSING CALLS TO FUNCTION FROM COMMON CODE BLOCKS
SWD COMMUNICATION FAILURE ON LPC11XX DEVICE
SWD COMMUNICATION FAILURE ON STELLARIS BOARD
SWITCH/CASE STATEMENTS
SYMBOL NAMES LONGER THAN 32 CHARACTERS
SYMBOL VS PUBLIC VARIABLES
SYMBOLS DIRECTIVE
SYMBOLS DIRECTIVE
SYNTAX ERROR WHEN DECLARING A VARIABLE
SYSTEM ARCHITECTURE AND ASSEMBLY PROGRAMMING
SYSTEM STACK LARGER IN RL-ARM?
SYS_ERROR (ERR_MEM_FREE) CALLED
Section 2.1. Multimedia Card Specification
Section 2.1. Single Versus Dual AHB Master Interface
Section 2.10. Burst Requests
Section 2.11. DMAC Channels
Section 2.12. DMAC Programming
Section 2.13. Synchronization
Section 2.14. Endianness
Section 2.15. Address Generation
Section 2.16. Linked Lists
Section 2.17. DMAC Usage Scenarios
Section 2.18. Setting Up The DMAC For A Transfer
Section 2.2. MMCI Clocks
Section 2.2. Protection Information
Section 2.3. Burst Size - Source and Destination
Section 2.3. FIFOs
Section 2.4. Accesses to the MMCI
Section 2.4. Source and Destination Transfers
Section 2.5. MMCI Commands
Section 2.5. Transfer Size
Section 2.6. Difference Between Width of Transfer and Burst Size
Section 2.6. Off-Chip MMCI Signals
Section 2.7. Endianness
Section 2.7. SINGLE versus BURST DMAC Transfers
Section 2.8. Burst Transfers
Section 2.8. MMCI Interrupts
Section 2.9. Flow Control
Section 2.9. STOP COMMAND
Serial Wire Debug sequence fails to produce WAIT responses for wait-states then generates WDATAERR
Server cannot start because of 'java.io.IOException: Keystore was tampered with, or password was incorrect'
Server cannot start because of 'java.security.UnrecoverableKeyException: Cannot recover key'
Server log reports "Invalid license key (inconsistent authentication code)"
Set $top_of_memory to match target board memory
Setting Conditional Breakpoints
Setting push url always fails
Sharing header files between C and assembler
Should a slave respond with an error or OKAY response when the user addresses memory space in the slave that has no registers?
Should my revision D EB have a solder bridge on IC U92?
Should slaves/bridges which have some form of write buffer capability also include forwarding logic to return the result of a read transaction when a write to the same location is stored in the write buffer?
Should the AHB and APB interfaces on Mali-55 be clocked on the same frequency?
Should the protection/cache information for address regions be consistent between read and write operations?
SimpleCADI
Some ARM cores are capable of generating transfers on the AHB which are non bufferable. Is it mandatory to support this when designing bridges which interface to the AHB (i.e. bridges which do not buffer writes)?
Some examples to compare Microlib vs. Stdlib
Split/Retry: Can a SPLIT or RETRY response be given at any point during a burst?
Split/Retry: Can a slave assert HSPLITx in the same cycle that it gives a SPLIT response?
Split/Retry: Can a slave use both SPLIT and RETRY responses?
Split/Retry: Do all masters have to support SPLIT and RETRY?
Split/Retry: Do all slaves have to support the SPLIT and RETRY responses?
Split/Retry: What address should be on the bus during the IDLE cycle after a SPLIT or RETRY?
Split/Retry: What is the difference between SPLIT and RETRY responses?
Split/Retry: What value should be used for HTRANS when an AHB master gets a RETRY response from a slave in the middle of burst?
Split/Retry: Will a master always lose the bus after a SPLIT response?
Support for non-ISO C++ Syntax in RVCT
Synchronous Watchpoint from SystemC
TAB CHARACTERS ARE EXPANDED TO SPACE CHARACTERS
TABLES WITH CALCULATED VALUES
TABS - UNKNOWN CONTROL
TAP order when using manual configuration
TARGET AND LOCATE DIALOG RELATIONSHIP
TARGET NOT CREATED - CAN'T EXECUTE MESSAGE
TARGET SYSTEM DOES NOT RESPOND
TARGETING AN 8051
TASK EXECUTION AFTER HIGH-PRIORITY TASK
TASK EXECUTION AFTER INTERRUPT
TASK WITH PRIORITY 3 REQUIRES REGISTERBANK
TASKS 0 RUNS BUT OTHER TASKS DON'T
TASKS NEVER START
TCP/IP COMMUNICATIONS UNSTABLE ON PHYCORE229X
TCP/IP DEBUGGING WITH RL-ARM
TCP/IP SUPPORT
TCPNET SUPPORT FOR IPV6
TECHNICAL SUPPORT EXPIRED MESSAGE ON INSTALLATION
TECHNICAL SUPPORT FOR ANCHOR CHIPS
TESTING CAN PROGRAMS
TESTING VON NEUMANN MEMORY AREAS
TEXT EDITOR DOESN'T AUTOMATICALLY INDENT
THE CODE BANKING MECHANISM
THIS PROGRAM CANNOT BE RUN IN DOS MODE
TIMEOUT ERRORS WHEN STARTING DEBUG MODE
TIMING AND DELAY FUNCTIONS
TINY DIRECTIVE
TIPS
TOOL PATH NOT DEFINED ERROR
TRACE DATA LOST OR WRONG
TRAFFIC2 EXAMPLE GENERATES WARNINGS
TRANSFER FONT SETTINGS AND TOOLS MENU ENTRIES
TRANSFERRING CONTROL FROM BOOT LOADER TO APPLICATION
TRANSITION FROM OS_STK_OVERFLOW() TO OS_ERROR()
TRANSLATE FILE DOESN'T WORK
TRANSLATION OF START_V2.A66 FAILS
TRANSMITTING FLOATING-POINT NUMBERS
TROUBLE WITH FLASH PROGRAMMING
TURNING OFF WARNINGS
TYPEDEF ENUM
The ARM core itself has a lot of debug pins which are not routed out of the ARM AHB wrapper block (e.g. EXTERN, RANGEOUT, DBGACK, BREAKPT,...). Are they really necessary or is it sufficient to use the JTAG port only?
The ARM720T has both nOPC and BPROT[0] signals. According to the datasheet, both indicate opcode fetches. What is the difference between the two signals and what are they used for? (Rev 0-3)
The ARMv7-M ARM describes address 0xE000E000 as the SCS, but the TRM and IIM describe it as the NVIC. Which is it?
The BuildCORTEXM7_DSM.pl script fails with a syntax error at line 169, near ""DSM_gen" ~"
The Ethernet interface on my Integrator/CP has stopped working
The Ethernet interface on my PB926/AB926 board has stopped working
The L2 data RAM clock becomes X during MBIST mode.
The Multi-ICE unit model number 83 needs a jumper fitted to be powered from the target board
The register offset addresses do not match up between the TRM and the RTL. Why?
The specification mentions that AxPROT[2] information is just a hint. Is the information given by the other AxPROT bits always accurate?
There is a feature called "Deep Power Down" with Mobile SDRAM which cuts the power off the memory cells in Mobile SDRAM. Is this feature supported with PL340?
There is a new signal for ARM720T rev 3, called CACHEDIS. How should I use this?
Topology detection with the CoreSight Trace Funnel
Trapping and identifying divide-by-zero errors
Trapping and identifying divide-by-zero errors
Trouble shooting floating license issues
Trouble shooting node-locked license issues
UART OR LIN DOES NOT WORK
ULINK - CANNOT STOP ARM DEVICE!
ULINK DOES NOT ERASE ALL SECTORS
ULINK-ME FAILS WITH ACTEL SMARTFUSION BOARDS
ULINK2 ADAPTER NOT RECOGNIZED
ULINK2 DOES NOT FIND TARGET DEVICE
ULINKPRO DOESN'T DETECT DRIVER
UN-ALIGN ACCESS GIVES UNEXPECTED RESULTS
UNABLE TO BUILD INDIVIDUAL GROUPS
UNABLE TO DEFINE INTERRUPTS - CODE SPACE OVERLAP
UNABLE TO FIND INCLUDE FILES USING LONG DIRECTORY NAMES
UNABLE TO REGISTER PRODUCT SERIAL NUMBER (PSN)
UNABLE TO REPROGRAM PHILIPS 89LPC932
UNABLE TO SIMULATE INTERRUPTS
UNDEFINED MC SYMBOLS IN FS_FAT.O
UNDEFINED SPI SYMBOLS IN FS_LIB.O
UNICODE, WIDE CHARACTER, & ASIAN CHARACTER SUPPORT
UNINITIALIZED VARIABLES GET INITIALIZED
UNION INVOLVING A BITFIELD IS THE WRONG SIZE
UNKNOWN DATA AT END OF IMAGE
UNLOCKING FREESCALE KINETIS MEMORY WITH ULINK
UNRESOLVED EXTERNAL ?C?CLDOPTR
UNRESOLVED EXTERNAL ERROR USING ASSEMBLER AND C
UNRESOLVED EXTERNAL SYMBOL '?C?LIMUL'
UNRESOLVED EXTERNAL SYMBOL ?C?INIT
UNRESOLVED EXTERNAL SYMBOL ?C?XPAGE1SFR
UNRESOLVED EXTERNAL SYMBOL FOR MATH AND FP ROUTINES
UNRESOLVED EXTERNAL WITH FAR MEMORY TYPE
UNRESOLVED EXTERNALS WITH OS CALLS
UNRESOLVED SYMBOL ?C_STARTUP
UNRESTRICTED VERSION BEHAVES AS RESTRICTED VERSION
UNSIGNED_CHAR DIRECTIVE
UNUSED OPCODES
UNUSUAL CHARACTERS IN FILENAMES
UPDATE PROJECT EXCLUDES CHANGED HEADER FILES
UPDATES FOR PK161
UPDATING A LICENSE(LIC)
UPDATING LPC TOOLCHAIN
UPDATING SERIAL NUMBER AFTER RENEWING
UPDATING THE PROGRAM COUNTER ON THE STACK
UPGRADED TO WINDOWS NT/2000 AND PROTECTION FAILS
UPGRADING BETA RELEASES
UPSD3233 HAS INCORRECT XRAM RANGE
USB CONNECTION IS LOST ON WINDOWS 98
USB DONGLE NOT RECOGNIZED
USB DRIVER FOR ULINK / EPM900
USB ENUMERATION EXAMPLE LINKS WITH ERRORS
USB EXAMPLES DO NOT WORK
USB HID AND MASS STORAGE DEVICE EXAMPLES DO NOT WORK
USB INTERFACE FOR KEIL MONITOR
USB LED OR USBCV TEST FAILS
USB OTG support on PB11MPCore, PB1176JZF-S and PB-A8
USB PROBLEMS
USB SECURITY KEY DOES NOT WORK ON WINDOWS98/ME/NT4
USB SUPPORT FOR THE INTEL 930
USB TO SERIAL CONVERTER DOES NOT WORK
USB-COM DRIVER DOES NOT INSTALL
USE ADD-ON DISKETTE WITHOUT DISKETTE DRIVE
USE AS A SELF-POWERED USB DEVICE
USE DONGLE WITH PORT EXTENSION CARD ON PCI BUS
USE DOXYGEN FOR AUTOMATED CODE DOCUMENTATION
USE IN ASSEMBLER PROGRAMS
USE OF DUAL DATA POINTERS
USE OF F0 AND F1 IN PSW
USE SPECIFIC ADDRESS RANGE FOR MOVC
USER APPLICATION OUTPUT MISSING
USER INTERRUPT FUNCTION DOES NOT WORK
USER PROGRAM EXECUTION FAILS
USER STACK POINTER ADDRESSING VIA DPP3
USER'S GUIDE ERRORS
USERCLASS DIRECTIVE
USERSTACKDPP3 DIRECTIVE
USING #IF TO TEST CONDITIONS
USING 'AT' RELOCATION TYPE WITH SEGMENT DIRECTIVE
USING / AND IN PATHNAMES
USING 1K SRAM ON DALLAS DS89C420
USING 2 STRUCTS THAT HAVE POINTERS TO EACH OTHER
USING 24-BIT MATH WITH FAR POINTERS
USING 2ND SERIAL PORT (ASC1) ON INFINEON XC16X DEVICES
USING 2ND SERIAL PORT (ASC1) ON THE INFINEON C161CS
USING > 64KB EXTERNAL SRAM WITH C8051F12X DEVICES
USING A BOOTLOADER ON AN AT91SAM7
USING A WATCHDOG TIMER DURING DEBUGGING
USING AN EXTERNAL EDITOR
USING AUTO-DECREMENT/AUTO-TOGGLE WITH DALLAS 390 & 400
USING BOTH ASC0 AND ASC1 ON THE INFINEON C161CS
USING C SFR AND SBIT DEFINITIONS
USING C51 V7.50 WITH A C51 V8 PSN
USING CAN WITH THE C505C & C515C
USING CODE BANKING
USING COM0
USING DEBUG TRACE ON ACTEL A2F200 BOARDS
USING DEFINE TO SPECIFY AN #INCLUDE FILE
USING DONGLES WITH LPT2 OR LPT3
USING DONGLES WITH WINDOWS NT/2000
USING DONGLES WITH WINDOWS NT/2000
USING DONGLES WITH WINDOWS NT/2000
USING DPP1 AND DPP2 IN ASSEMBLER ROUTINES
USING DRK REGISTERS WITH IMMEDIATE VALUES
USING ECRM MODE ON PHILIPS MX2
USING EMBEDDED C++
USING EXTENDED BIT AREAS
USING FUNCTION POINTERS WITH CODE BANKING
USING HEX2BIN WITH HEX FILES
USING HVAR OR XVAR GENERATES BAD EXTS SEQUENCES
USING IDLE MODE ON STR9 WITH RTX KERNEL
USING INTERRUPT NESTING
USING INTERVAL AND FIXED WAIT TIMES
USING LARGE XDATA AND CODE BLOCKS
USING LIBRARY FUNCTIONS
USING LPC2378 ETHERNET MEMORY AS RAM
USING LX51 IN A CODE BANKED APPLICATION WITH STM UPSD3XXX
USING MACROS WITH IN-LINE ASSEMBLY
USING MCB900 WITH A FULL C51 PACKAGE
USING MDK-ARM ON LINUX
USING MDU_F120 AND MDU_R515 IN UVISION
USING MEMORY FROM 00H TO 1FH
USING MEMORY-MAPPED DEVICES
USING MICROCONTROLLERS WITH ON-CHIP XDATA
USING MON51 ON ADUC83X DEVELOPMENT BOARDS
USING MON51 WITH FLASH-ONLY DEVICES
USING MORE THAN 2K OF CODE SPACE
USING MOVX TO UPDATE FLASH ON C8051F320
USING MULTI-FUNCTION PINS ON ATMEL AT89C51RD2
USING MULTIPLE COMPILER VERSIONS
USING MULTIPLE DPTR
USING MULTIPLE PROJECT-SPECIFIC LIBRARIES
USING MULTIPLE PROJECT-SPECIFIC LIBRARIES
USING NON-REENTRANT FUNCTION IN MAIN AND INTERRUPTS
USING NOOVERLAY WITH UVISION2
USING NOP IN C
USING OFF-CHIP UART INTERFACES
USING ON-CHIP AND OFF-CHIP FLASH ON PHILIPS ARM
USING ONLY ONE REGISTERBANK
USING OS_WAIT AND OS_SEND_SIGNAL
USING PARTS NOT LISTED IN THE DEVICE DATABASE
USING PDATA MEMORY
USING PDATA ON ADUC83X AND ADUC84X DEVICES
USING PDATA VARIABLES ON INFINEON XC800
USING PHILIPS MX DEVICE WITH C51 / BL51
USING PRINTF WITH GNU
USING PRINTF, SPRINTF, SCANF, AND SSCANF
USING PROROM WITH UVISION2
USING REGISTERBANKS AND INTERRUPTS
USING REGISTERS WHEN CALLING AN ASSEMBLER FUNCTION
USING RL-FLASH FS WITH SECTOR SIZES LESS THAN 256 BYTES
USING ROM LIBRARY IN INFINEON XC8XX DEVICES
USING RTX TOGETHER WITH STM32 LIBRARY
USING SAM-ICE WITH UVISION
USING SBIT IN EMBEDDED C++
USING SECONDARY JTAG ON PHILIPS LPC2106
USING SERIAL INTERFACE DURING MONITOR DEBU
USING SERIAL PORT 1 WITH THE MSC1210
USING SETJMP AND LONGJMP WITH CODE BANKING AND RTX51
USING SFR16 FOR 16-BIT SFRS
USING SIO0 AND SIO1 WITH THE DALLAS 320
USING SOF FOR PEC IN EMBEDDED C++
USING SRC FILES ALWAYS FORCES A RECOMPILE
USING SWI_VEC.S WITH ARTX-ARM
USING THE ! MACRO OPERATOR
USING THE 517 MULTIPLY/DIVIDE UNIT IN INTERRUPTS
USING THE AINX VTREGS
USING THE BROWNOUT VTREG
USING THE C509 MULTIPLY/DIVIDE UNIT
USING THE CODEWRIGHT EDITOR
USING THE CODEWRIGHT EDITOR
USING THE DS87C520 INTERNAL SRAM
USING THE ENTER COMMAND
USING THE FLASH MENU
USING THE FULL 256K MEMORY SPACE
USING THE MVAR MACRO FOR FIXED VARIABLE LOCATION
USING THE ON-CHIP RAM OF THE INFINEON C167CR
USING THE ON-CHIP XDATA OF THE INFINEON C515C
USING THE OS_ENABLE_ISR FUNCTION
USING THE PHILIPS 87C751
USING THE PORTX VTREGS
USING THE RC OSCILLATOR FOR PHILIPS LPC CH
USING THE RWATCH BUILT-IN FUNCTION
USING THE SIMULATED SERIAL PORT
USING THE SIN VTREG
USING THE SOUT VTREG
USING THE STACK FOR ALL LOCAL VARIABLES
USING THE STIME VTREG
USING THE SVCS MENU
USING THE SWATCH BUILT-IN FUNCTION
USING THE TI MSC1210-DAQ-EVM BOARD
USING THE TWATCH BUILT-IN FUNCTION
USING THE UV2 MON51 WITH THE CYPRESS CY3671
USING THE WWATCH BUILT-IN FUNCTION
USING THE _ATOMIC_ FUNCTION
USING THIRD-PARTY PLUG-INS
USING TIMED ACCESS REGISTERS ON DALLAS PARTS
USING TRACE MEMORY WITH THE MONITOR
USING TWO DIFFERENT TOOL CHAIN VERSIONS
USING ULINK AS A DEVICE PROGRAMMER
USING ULINK WITH ATMEL AT91 DEVICES
USING ULINK2 ON LPC2000 DEVICES
USING ULINKME WITH CAN APPLICATIONS
USING VERSION 3 COMPILER WITH VERSION 4 LIC
USING VERSION 6.12 WITH A VERSION 8 INSTALLATION
USING WILDCARDS IN SEGMENT NAMES
USING WITH DEVICES WITH EXTERNAL PROGRAM LOCK BITS
USING WITH SILABS SFR PAGING
USING XC16X FAST INTERRUPTS
USING XC16X FAST REGISTER BANK SWITCHING
USING XHUGE POINTERS WITH LIBRARY ROUTINES LIKE STRCPY
USING XRAM ON THE PHILIPS 80C66X AND 80C51RX DEVICES
UTILITY FOR COMBINING INTEL HEX FILES
UTILITY FOR COMBINING INTEL HEX FILES
UTILITY FOR COMBINING INTEL HEX FILES
UV2 DEBUGGER AND TRISCEND E5 - OUTPUT FILE DOWNLOAD
UV4.EXE IS NOT A VALID WIN32 APPLICATION
UVISION CRASHES WHEN CHANGING SETTINGS OF EPM900
UVISION DEBUGGER: UNEXPECTED DEBUGGER EXIT
UVISION TREATS LIBRARY FILE AS ASSEMBLY FILE
UVISION USER'S GUIDE MISSING
UVISION2 C51 UPGRADE VS. UVISION3 DEMO?
UVWINRUN TEST VERSION DETAILS
Unable to access TPIU registers, they appear to be stuck at zero
Unable to program the Data Watchpoint Unit / Data Watchpoint and Trace Unit (DWT)
Undefined Instruction in "_fp_init()"
Unexpected memory behavior at addresse ranges 0x22xxxxxx, 0x23xxxxxx, 0x42xxxxxx or 0x43xxxxxx
Unrecognized option '--elf' when attempting to build Linux applications with RVCT 3.1 evaluation version
Unrecognized option '--no_depend_system_headers' when building Eclipse projects
Unstable behaviour when multiple projects are open in RVD
Unused top level files in Cortex-A5
Updated connectivity_spreadsheet.xls for the V2F-1XV7 logic tile
Updated gateway.dll supports hardware-assisted vector-catch
Updating an ADS 1.1 License Server to license ADS version 1.2 features
Updating an ADS License Server to license RVDS features
Use of 'const' and 'volatile'
Use of --asm with RVDK for OKI
Use of --fpu softvfp with processors with implicit VFP
Use of Synchronous Serial Port (PL022) on the AB926
Use of banked registers after forced user-mode STM
Use of other parallel port devices when Multi-ICE is installed
Using CT11MPCore + EB: Can I use Xilinx Chipscope?
Using CT11MPCore + EB: How are interrupts routed?
Using CT7TDMI + EB: Boot Monitor will not display in RVD 'StdIO' pane
Using CT926 + PB926: How do I identify which core is which on the JTAG scan chain?
Using Multi-ICE with the Texas Instruments TMS470 processor
Using ULINKpro on the STM3240G-EVAL Board
Using the Inline Assembler
V1.31 UPDATE CRASHES
V2.12 STARTUP CODE PROBLEMS
V3.11 BUG CORRECTIONS
V3.11 NDATA/NCONST SIZE EXCEEDS 16KB MESSAGE
V4.06 UPDATE SAYS V4.05
V6.0 INSTALLATION PROBLEMS WITH CD-ROM RELEASE 12.99
V6.00 OPTIMIZATIONS CAUSE LINKER ERRORS/WARNINGS
V6.02 UPDATE SAYS V6.01
V7.50 USES TOO MUCH SPACE FOR FAR CONST DATA
VALID VALUE ASSIGNMENT CREATES WARNING
VARIABLE ACCESS FROM C
VARIABLE ALIGNMENTS AND EVEN DIRECTIVE
VARIABLE BANKING CONFIGURATION OPTIONS
VARIABLE DISPLAY PROBLEMS WITH LX51 LINKER
VARIABLE INITIALIZATION HALTS PROGRAM EXECUTION
VARIABLE ORDERING
VARIABLE RANGES
VARIABLE ZERO INITIALIZIATION
VARIABLES CREATED IN XDATA USING SMALL MODEL
VARIABLES DO NOT GET INITIALIZED WITH GNU C
VARIABLES DON'T DISPLAY IN LOCAL WATCH WIN
VARIABLES GET LOCATED TO RW RATHER THAN ZI
VARIABLES IN LARGE AND COMPACT MEMORY MODEL DON'T WORK
VARIABLES IN NON-VOLATILE MEMORY
VARIABLES NOT KEPT IN ORDER
VARIABLES WITH THE SAME NAMES AS KEIL KEYWORDS
VECTOR CHECKSUM FOR NXP LPC2000 DEVICES
VECTOR FLOATING POINT UNIT ON LPC3000
VERIFY OPTIONS WITH UPSD DEVICES
VERIFYING LOOK-UP TABLE VALUES
VERSION 2 LINKER ACTS LIKE EVALUATION VERSION
VERSION 2.14 RELEASE NOTES
VERSION 3 RELEASE NOTES
VERSION 4 RELEASE NOTES
VERSION 4 RELEASE NOTES
VERSION 4.01 UPDATE PROBLEMS
VERSION 6 RELEASE NOTES
VIEWING GPIF REGISTERS ON CY3671 EZ-USB FX
VIEWING HIGH LEVEL SOURCE CODE IN LIBRARIES
VIRTUAL FUNCTION POINTERS IN DIFFERENT MEMORY SPACES
Versatile Baseboard USB Debug/Programming port does not work
Virtualization Example
WAIT FOR MESSAGE + SIGNAL
WAIT STATE B ( WSB ) VS EXTENDED DATA FLOAT ( EDF )
WARNING 1 (UNRESOLVED EXTERNAL SYMBOL)
WARNING 1 (UNRESOLVED EXTERNAL SYMBOL) USING SBITS
WARNING 2 (REFERENCE MADE TO UNRESOLVED EXTERNAL)
WARNING 2 (REFERENCE MADE TO UNRESOLVED EXTERNAL...)
WARNING 3 (ASSIGNED ADDRESS NOT COMPATIBLE)
WARNING 4 (DATA SPACE MEMORY OVERLAP)
WARNING 4 (DATA SPACE MEMORY OVERLAP)
WARNING 5 (CODE SPACE MEMORY OVERLAP)
WARNING 5 (CODE SPACE OVERLAP)
WARNING 6 (MEMORY SPACE OVERLAP)
WARNING 6 (XDATA MEMORY SPACE OVERLAP)
WARNING 6 (XDATA MEMORY SPACE OVERLAP) USING _AT_
WARNING 6 (XDATA SPACE MEMORY OVERLAP)
WARNING 7 (MODULE NAME NOT UNIQUE)
WARNING 7 (MODULE NAME NOT UNIQUE)
WARNING 7 (MODULE NAME NOT UNIQUE)
WARNING 8 (MODULE NAME EXPLICITLY REQUESTED FROM ...)
WARNING 9 (EMPTY ABSOLUTE SEGMENT)
WARNING #61-D: INTEGER OPERATION RESULT IS OUT OF RANGE
WARNING 10 (CANNOT DETERMINE ROOT SEGMENT)
WARNING 11 (CANNOT FIND SEGMENT OR FUNCTION NAME)
WARNING 12 (NO REFERENCE BETWEEN SEGMENTS)
WARNING 13 (RECURSIVE CALL TO SEGMENT)
WARNING 13 (RECURSIVE CALL TO SEGMENT)
WARNING 14 (INCOMPATIBLE MEMORY MODEL)
WARNING 140 (FUNCTION UNDEFINED, ASSUMING...)
WARNING 15 (MULTIPLE CALL TO SEGMENT)
WARNING 15 (MULTIPLE CALL TO SEGMENT)
WARNING 16 (UNCALLED SEGMENT)
WARNING 16 (UNCALLED SEGMENT, IGNORED FOR OVERLAY ...)
WARNING 16 (UNCALLED SEGMENT, IGNORED FOR OVERLAY ...)
WARNING 16 (UNCALLED SEGMENT...) FOR CALLED FUNCTION
WARNING 17 (INTERRUPT FUNCTION IN BANKS NOT ALLOWED)
WARNING 173 (MISSING RETURN-EXPRESSION)
WARNING 182 (POINTER TO DIFFERENT OBJECTS)
WARNING 185 (DIFFERENT MEMORY SPACE)
WARNING 189 (STORAGE CLASS CHANGED TO STATIC)
WARNING 19 (COMMON CODE SEGMENTS ...)
WARNING 19 (COMMON CODE SEGMENTS ...)
WARNING 196 (MSPACE PROBABLY INVALID)
WARNING 198 (SIZEOF RETURNS ZERO)
WARNING 20 (NBANKS LESS THAN # OF CODE BANKS), PT 1
WARNING 20 (NBANKS LESS THAN # OF CODE BANKS), PT 2
WARNING 206 (MISSING FUNCTION PROTOTYPE)
WARNING 209 (TOO FEW ACTUAL PARAMETERS)
WARNING 219 (LONG CONSTANT TRUNCATED TO INT)
WARNING 22 (CLASS RANGE NOT GIVEN)
WARNING 23 (NDATA MUST FIT IN ONE 16K PAGE)
WARNING 23 (NDATA OR NCONST MUST FIT IN ONE 16K PAGE)
WARNING 245 (UNKNOWN PRAGMA, LINE IGNORED)
WARNING 258 (MSPACE ILLEGAL ON STRUCT/UNION MEMBER)
WARNING 259 (POINTER: DIFFERENT MSPACE)
WARNING 259 (POINTER: DIFFERENT MSPACE)
WARNING 260 (POINTER TRUNCATION)
WARNING 261 (BIT IN REENTRANT FUNCTION)
WARNING 265 (RECURSIVE CALL TO NON-REENTRANT FUNCTION)
WARNING 271 (MISPLACED ASM/ENDASM CONTROL)
WARNING 275 (EXPRESSION WITH POSSIBLY NO EFFECT)
WARNING 276 (CONSTANT IN CONDITION EXPRESSION)
WARNING 277 (DIFFERENT MSPACES TO POINTER)
WARNING 280 (UNREFERENCED SYMBOL/LABEL)
WARNING 307 (MACRO 'NAME': PARAMETER COUNT MISMATCH)
WARNING 317 (MACRO 'NAME': INVALID REDEFINITION)
WARNING 317 (REDEFINITION OF MACRO)
WARNING 322 (UNKNOWN IDENTIFIER)
WARNING 323 (NEWLINE EXPECTED EXTRA CHARACTERS FOUND)
WARNING 324 (PREPROCESSOR TOKEN EXPECTED)
WARNING 500 (BAD OR MISSING COMPILER OVERLAY)
WARNING 500 -MISSING DEVICE (DRIVER NOT INSTALLED)
WARNING A130 (AMBIGOUS INSTRUCTION)
WARNING C192 (VALUE TRUNCATED)
WARNING C258 (MSPACE ON PARAMETER IGNORED)
WARNING C259 (DIFFERENT ENUMERATION TYPES)
WARNING C500 (MISSING DEVICE) AFTER UPDATE
WARNING DIRECTIVE
WARNING L1 (UNRESOLVED EXTERNAL SYMBOL)
WARNING L1 (UNRESOLVED EXTERNAL) USING INLINE ASSEMBLY
WARNING L13 (RECURSIVE CALL TO SEGMENT) WITH CONSTANTS
WARNING L16 (UNCALLED FUNCTION)
WARNING L16 (UNCALLED FUNCTION) USING CODE BANKING
WARNING L16 (UNCALLED SEGMENT) ?C_INITSEG
WARNING L16 (UNCALLED SEGMENT, IGNORED FOR OVERLAY)
WARNING L25 (DATA TYPES DIFFERENT)
WARNING L25 (DATA TYPES DIFFERENT) USING MEMCCPY
WARNING L34 (PROJECT DOES NOT INCLUDE LP51BANK MODULE)
WARNING L43 USING SRC MODE WITH PHILIPS MX
WARNING: L6306W: '~PRES8' SECTION SHOULD NOT USE 'REQ8'
WARNINGLEVEL DIRECTIVE
WARNINGLEVEL DIRECTIVE
WARNINGS SUPPRESSED FOR SYSTEM INCLUDE DIR FILES
WATCH THE IO-PORTS OF CYPRESS USB CONTROLLER
WATCH VARIABLES DO NOT DISPLAY
WATCH WINDOW CONTENTS ARE INCORRECT
WATCHDOG REFRESH
WATCHDOG REFRESH WHEN USING MONITOR
WATCHDOG RESET SIMULATING SILABS DEVICE
WATCHDOG RESETS EWT BIT IN SIMULATOR
WATCHING ASSEMBLY VARIABLES
WEB SITE ACCESS SPEED
WFI instruction doesn't work with inline assembler
WHAT APPLICATION NOTES ARE AVAILABLE?
WHAT ARE SEMAPHORES?
WHAT ARE THE LATEST VERSION NUMBERS?
WHAT ARE THE LIMITS FOR FLOATING-POINT NUMBERS?
WHAT ARE THE NEW SETTING OPTIONS FOR THE SIMULATOR
WHAT ARE _DATA_GROUP_ AND _BIT_GROUP_?
WHAT ARE {CVTB} CODE SECTIONS?
WHAT C51 KIT SHOULD I BUY TO WORK WITH CYPRESS EZ-USB
WHAT CAN CONTROLLERS ARE SUPPORTED?
WHAT CAN CONTROLLERS ARE SUPPORTED?
WHAT CAUSES HEX FILES TO CHANGE BETWEEN VERSIONS?
WHAT CHIPS ARE SUPPORTED IN VERSION 4?
WHAT CHIPS ARE SUPPORTED?
WHAT DEVICES ARE SUPPORTED?
WHAT DO THE CODE COVERAGE COLORS MEAN?
WHAT DOES OS_WAIT(K_TMO, 0, 0) DO?
WHAT DOES P1.0 DO?
WHAT DOES THE CONFIGURATION WIZARD DO?
WHAT FILE TYPES ARE CREATED?
WHAT FILE TYPES DOES UVISION3 SUPPORT?
WHAT FILES ARE LEFT ON THE CD-ROM
WHAT HAPPENED TO ANCHORCHIPS?
WHAT HAPPENED TO SIEMENS?
WHAT IF I MAKE A MISTAKE WHILE LICENSING?
WHAT IS ?C?LIB_DATA USED FOR?
WHAT IS A CID?
WHAT IS A FLOATING-POINT OPERATION?
WHAT IS PAGE MODE VERSUS NON-PAGE MODE?
WHAT IS R0 USED FOR?
WHAT IS THE ADDRESS RANGE ACCEPTABLE BY XBYTE MACRO
WHAT IS THE PURPOSE OF $MODEL
WHAT IS THE _XDATA_GROUP?
WHAT'S IN THE .I FILE?
WHAT'S IN THE ?CO? SEGMENTS?
WHAT'S INCLUDED?
WHAT'S THE BEST WAY TO DISABLE/REENABLE INTERRUPTS
WHAT'S THE DIFFERENCE BETWEEN CX51 AND C51?
WHEN ARE FUNCTIONS REENTRANT
WHEN SHOULD I USE RVDS?
WHEN/WHERE ARE GLOBAL AND STATIC VARIABLES INITIALIZED?
WHERE ARE THE LATEST UPDATES?
WHERE ARE THE PRODUCT UPDATES?
WHERE CAN I FIND MORE INFORMATION?
WHERE CAN I GET A MANUAL?
WHERE CAN I GET SAMPLE CODE FOR THE 89LPC9XX SERIES
WHERE IS THE ABSOLUTE OMF OBJECT MODULE?
WHERE IS THE PROROM EPROM EMULATOR?
WHERE IS THE USER STACK LOCATED?
WHERE TO FIND THE ULINK2 DRIVER
WHERE TO FIND UPDATES
WHERE TO GET MORE INFORMATION
WHERE'S THE TE5_UV2.DLL FOR FASTCHIP 2.4.0
WHICH 8051-BASED CHIPS ARE SUPPORTED?
WHICH STARTUP CODE TO USE
WHICH SYSTEM FUNCTIONS ALLOW A TASK SWITCH
WHILE STATEMENT
WHY AREN'T THE LATEST UPDATES ON THE WEB?
WHY DO MOST KEIL EXAMPLES USE THUMB MODE?
WHY DOES C51 V6.01 INCLUDE C51 V5.50A?
WHY DOES VA_ARGS WORK?
WHY NUMBER OF BYTES PASSED TO PRINTF IS LIMITED
WHY SHOULD I USE PAGE MODE?
WIDE CHARACTER SUPPORT
WIDE CHARACTER SUPPORT
WIDE CHARACTER SUPPORT
WIDTH OF THE MEMORY WINDOW
WILL MY 8051 CODE WORK WITH THE 251?
WILL NOT CREATE HEX FILE
WILL OS_WAIT (K_SIG + K_TMO...) WORK?
WILL RTX51 VERSION 7 WORK WITH C51 VERSION 5?
WINDOWS COMPATIBILITY
WINDOWS 2000 COMPLIANCE
WINDOWS NT CANNOT FIND CTL3DV2.DLL
WINDOWS NT INSTALLATION PROBLEMS
WINDOWS VISTA CAN NOT FIND ULINK DRIVER
WORD VARIABLES ON ODD-BYTE BOUNDARIES
WORKAROUND FOR P89C669 CORE.2 ERRATA
WORKBOOK MODE FOR TEXT FILE EDITING
WORKING WITH ARM REALVIEW TOOLS
WORKING WITH ISD51
WRITING INTERRUPT ROUTINES
WRITING RELOCATABLE C FUNCTIONS FOR COPYING TO RAM
WRITING TO PORT 1 CAUSES PROBLEMS WITH DEBUGGER
WRITING TO THE OUTPUT PORTS
WRITING YOUR OWN CODE BANKING SYSTEM
WRONG CODE GENERATED FOR DOUBLE INDIRECTION
WRONG CODE IN DISASSEMBLY WINDOW
WRONG CODE WITH BIT-FIELD WIDTH EQUAL TO BASE TYPE
WRONG DRIVERS
WRONG HEADER FILE FOR PHILIPS P89C664
WRONG RESULT IN STRING ESCAPE SEQUENCES
WRONG RESULT WITH BINARY NOT AND UNSIGNED CHAR
WRONG TIMING WITH OS_ITV_SET()
WRONG WATCHDOG VALUES FOR ST UPSD33XX
Warning (IMG53): image.axf has no source level debug information
Warning (LUX47): The image does not match the target
Warning (LUX6): Unable to find library on host
We saw that the ARM7TDMI has two address bus connections. Do these pins need to be connected in layout or is a connection to a single pin enough?
We use Multi-ICE for debugging. We would like to reduce pin count in our system. Is it necessary to have separate connections for nTRST and core reset (nRESET/HRESETn/BnRES)?
We want to verify the (JTAG) debug system of the core in our simulation environment. Are there any prewritten test vectors/test benches available?
We've just received a new DSM: do I need to make any changes to my simulation environment to use it?
What AHB bus burst types are used by the ARM926EJ-S?
What AHB interfaces are on the ARM968E-S?
What AHB transactions will my ARM core generate?
What AHB-Lite burst lengths are produced by Cortex-M3 and Cortex-M4?
What AXI ID mapping does the PL310 r3p1 use ?
What AXI IDs can the PL310 master ports issue when the PL310 is disabled?
What AXI and AHB example designs are available for the LT-XC4V (Virtex-4) Logic Tile?
What AXI bus width should the Mali-200 be connected to ?
What AXI response value should be given by a slave which contains a mixture of secure and non-secure registers, when a non-secure access is attempted to a secure register?
What AXI response value should be given to a non-secure access to a secure address location?
What DSMs are available for the ARM968E-S ?
What ETMs are supported by which versions of TDT?
What JTAG connector should I specify if I wish to debug with RealView ICE?
What Streamline support is available for Android targets?
What address range does the AHBP bus occupy?
What are .mul files?
What are Overlays and how are they used?
What are STCALIB and STCLKEN or STCLK, and how should I connect them in the SoC?
What are errata 458693 and 460075 ?
What are imprecise aborts ?
What are my options regarding small and inexpensive evaluation boards and how do I get them?
What are the '.ngo' files provided in the Versatile and Versatile Express DVD?
What are the AHB bus transactions that PL080 can achieve?
What are the AHB interfaces ?
What are the LT-XC4V (Virtex-4) Logic Tile I/O connections?
What are the LT-XC5V (Virtex-5) Logic Tile I/O connections?
What are the MMD signals and how are they used?
What are the allowable byte lane strobes for fixed address burst?
What are the connectors on the Integrator/AM Analyzer Module?
What are the considerations when designing with an ARM hard macro clock?
What are the debug options on the ARM968E-S?
What are the differences between ARMv7-A, ARMv7-R and ARMv7-M?
What are the differences between GIC-390 and GIC-400?
What are the differences between PL110 and PL111?
What are the differences between RVCT for BREW 3.0 and the compilation tools in RVDS 3.0?
What are the differences between TDT 1.1 (1.1.1) and TDT 1.2?
What are the differences between a revision B and revision C EB?
What are the differences between the AHB Interfaces of the ARM9E family cores?
What are the differences between the ARM7TDMI-S and the ARM7TDMI?
What are the differences between the DMAEND and DMAKILL instructions?
What are the differences between the LT-XC2V (Virtex-II) and LT-XC4V (Virtex-4) Logic Tiles?
What are the differences in the revisions of the ARM720T?
What are the differences in the way the ARM VICs handle vectored and non-vectored interrupts?
What are the electrical parameters required for a CoreSight Debug / Trace port?
What are the main differences between ARM926EJ-S and ARM946E-S?
What are the metal layer constraints for LF072-ARM926EJ-SMIC 013G design kit ?
What are the nSRST and nTRST signals from the JTAG connector?
What are the possible values for ARLOCKP, AWLOCKP on ARM1176 ?
What are the requirements to meet before applying a Warm reset to a Cortex processor?
What are the restrictions on the type of image I can profile with RealView Profiler?
What are the restrictions when debugging the ARM968E-Srd core?
What are the timing requirements of interrupts entering the ARM core?
What are the types of encryption keys programmed into the Logic Tile?
What cache sizes can be used in the ARM926EJ-S Macrocell?
What can cause ARM11 not to enter standy mode when WFI instruction is executed?
What can cause a STICKYERR in a CoreSight Debug Access Port (DAP)?
What causes the TPIU to generate "trigger packet"
What causes the lockup_err bit to be asserted?
What code/data must be placed in a root region of a scatter file?
What combinations of INITRAM and VINITHI will allow booting from ITCM?
What compiler/linker options make a GNU-stack executable?
What differences are there between the ARM968E-S and the ARM966E-S (Rev 2) ?
What do "SafeCast Error 401 + 1", "SafeCast Error 407 + 1" and "SafeCast Error 408 + 1" mean?
What do CDBGRSTREQ / CDBGRSTACK, CDBGPWRUPREQ / CDBGPWRUPACK, CSYSPWRUPREQ / CSYSPWRUPACK actually do?
What do I do when an ARM Development Board, DSTREAM or RVI/RVT unit stops working or it has been received as DOA (Dead On Arrival)?
What do I set the ARM TAP IDCODE to?
What do each of the ARM7TDMI production test patterns cover?
What does "Address Reference Count" mean in the linker callgraph output?
What does "An error occurred during the installation of assembly..." mean when installing DS-5?
What does "Error: L6248E: cannot have address type relocation" mean?
What does "Error: L6286E: Value out of range for relocation" mean?
What does "Fatal error: L6815U: Out of memory" or "Error L6000U: out of memory"mean?
What does "TDMI-S" stand for?
What does "Warning L6932W: Library reports warning: use of helper library h_xx.l is deprecated" mean?
What does ARM stand for?
What does DSM stand for?
What does L210 do with AXI IDs when disabled?
What does PL330 do if there is insufficient data inthe MFIFO?
What does Progcards 'WARNING: No matches found between scan chain and board files' mean?
What does RealView ICE do in its boot sequence? / The RealView ICE boot sequence does not finish / LED B does not stop blinking
What does error "Cannot determine current address space as target is running, specify an explicit load offset" mean?
What does internal fault 0x5c282c or 0x1ac98e mean when building Linux applications using armcc?
What does it mean when the ARM720T model warns of an "Output violation"?
What does the ARM720T do when the cache is not enabled?
What does the ARM7TDMI core read/write when using non aligned addresses?
What does the I2S block in the LogicTile Express Technical Reference Manual (TRM) do, and how can I use it?
What does the __ESCAPE__ macro in the ARM compilation tools' header files do?
What does the error "The CodeWarrior IDE is licensed and a valid license was not found...." mean?
What does the menu option: Debug -> Memory/Register Operations -> Flash Memory Control allow me to do in RVD?
What does the mode parameter on the telnet_terminal model do?
What does the phrase 'the DMA interface cannot access the AHB bus' in the TRM mean ?
What earlier versions of ADS are included as part of RVDS?
What effect do asynchronous interrupt sources have on Cortex-M7?
What environment variables do the Fast Model Tools and Portfolio use (pre 5.0)?
What environment variables do the Fast Model Tools and Portfolio use?
What happens after an xTCMERR caused by Parity or ECC - retry or abort? What if the access was speculative?
What happens if a DMA block and the core try to access the same item in the DTCM ?
What happens if an interrupt occurs and the interrupt handler does not remove the interrupt?
What happens if an interrupt occurs as it is being disabled?
What happens if an interrupt occurs as it is being enabled?
What happens if the slave is keeping AWREADY low waiting for the write response to be accepted while the master is keeping BREADY low waiting for the address to be accepted by the slave?
What happens inside the ARM core when an exception occurs?
What happens when the EDBGRQ signal is asserted?
What happens when the base address of an MPU region is not aligned with the region's size in PMSAv6 and PMSAv7?
What image formats does RVD support?
What input data formats will PL111 accept?
What is "warning #223-D: function 'exp2' declared implicitly" and its implication?
What is C$$ddtorvec and are there any related issues?
What is CTIINTISR[1:0]?
What is Cycle Accurate trace?
What is EIS?
What is Error S0004 (Server): This operation has failed (no details)?
What is Microlib?
What is ModelGen?
What is RDI?
What is SWIFT?
What is a Progcards 'skip' file?
What is a leaf function?
What is a suitable number of floating license seats required for building my application?
What is an external interface?
What is iRM?
What is low latency mode ?
What is meant by the arrows in section 3.3, "Dependencies between the channel handshake signals"?
What is required to run systems created using the Fast Model Tools?
What is the ACLKEN signal?
What is the ARM7TDMI Serialised Test Procedure?
What is the CoreSight High Density Probe?
What is the Cortex-A7’s behavior if we turn-on the L1/L2 data cache read-allocate mode disable bits ?
What is the Endianness of the core after reset?
What is the EtmMuxDemux block?
What is the ID Code of a Cortex-M0 DAP or Cortex-M0+ DAP?
What is the JEDEC JEP-106 Manufacturer ID Code and how is it used?
What is the OpenVG RI ?
What is the Peripheral Port Remap Register for ?
What is the US customs export control ECCN code to use for Cortex-A processors ?
What is the advantage of using TEX remapping ?
What is the advantage of using super sections ?
What is the advantage of using the LDREX,STREX ARM V6 instructions for semaphore operations over a SWP ?
What is the advantage of using the core VIC port ?
What is the behavior when an exception occurs while executing a floating operation?
What is the cause of internal fault 0xf42b?
What is the cause of internal fault [0xabc3e8:410631]?
What is the clock architecture of the CT7TMDI + IM-LT3 + Integrator CP platform?
What is the correct JTAG IDCODE for my Cortex processor?
What is the correct value of "chip_nmbr" bits in direct cmd register to enter DPD state of all memory devices simultaneously with global CKE configuration?
What is the default (out of box) configuration for the L220?
What is the depth of the ITM FIFO?
What is the die size and how fast will the ARM7EJ-S run?
What is the difference between "RealView Developer Kit for OKI" and "RealView Developer Kit for OKI Evaluation"?
What is the difference between +TEXT and +RW and how are they used in scatterloading files?
What is the difference between ADS 1.2 and RVDS (RVCT) 3.0 Compilation Tools?
What is the difference between ADS 1.2 and RVDS (RVCT) 3.1 Compilation Tools?
What is the difference between ARM and A32, Thumb and T32?
What is the difference between ARM7 and ARMv7?
What is the difference between DAPEN and DBGEN?
What is the difference between HW and SW breakpoints?
What is the difference between L2C-310 r3 IDLE and CLKSTOPPED outputs ?
What is the difference between PL352 vs PL354? Can I use two PL352 instead of one PL354?
What is the difference between RVCT 2.0 and RVCT 2.0.1?
What is the difference between RVDS 4.1 and RVDS 4.1 Professional?
What is the difference between V2F-1XV7 RevB and RevC?
What is the difference between a von Neumann architecture and a Harvard architecture?
What is the difference between registration and registration update?
What is the difference between the evaluation of RVDS 4.1 and the full version of RVDS 4.1?
What is the effect of DAPABORT?
What is the fastest way to copy memory on a Cortex-A8?
What is the fault coverage figure for ARM7EJ-S?
What is the format of the Cortex-M4 tarmac.log file?
What is the function of the Issue stage in the ARM10/ARM11 cores ?
What is the function of the S_RETIRE_ST bit in the Debug Halting Control and Status Register (DHCSR)?
What is the gate count figures for ARM7EJ-S?
What is the gate-count of the PL310 (AXI Level 2 Cache Controller)
What is the impact of a failed instruction in the Mali200 pipeline? How many cycles of latency does a failed instruction introduce?
What is the implication of not balancing FCLK and HCLK when I lay out my ARM720T design? Are there any implications for synchronous and asynchronous clocking modes?
What is the interrupt handling flow for level-sensitive interrupts?
What is the latest version of MultiTrace?
What is the longest burst the ARM1176 can perform?
What is the maximum AXI burst length in PL341? How is this affected by the FIFO depths?
What is the maximum TCK frequency that I can set up with DSTREAM / RVI ?
What is the maximum TCK frequency that I can set up with Multi-ICE?
What is the maximum amount of data that PL330 can transfer at any one time on a single channel?
What is the maximum anti-aliasing that Mali-200 can do without performance loss?
What is the maximum baud rate achievable by the UART - the TRM says it's 460.8Kbits/s?
What is the maximum core frequency RealView Trace can capture at?
What is the maximum framebuffer and texture resolution supported by Mali-400 MP?
What is the maximum frequency of debug and trace clocks in a CoreSight design?
What is the medium-plus configuration of ETM9?
What is the minimum time to hold BnRES low on the ARM720T to correctly reset the core?
What is the nature of Big Endian mode in PL080?
What is the part number for the 38-pin mictor trace connector?
What is the performance of the branch prediction logic ?
What is the pinout for the PISMO2, SATA and HSSTP connectors on the LogicTile?
What is the pupose of ACP signals ARUSERS[4:0], AWUSERS[4:0] on Cortex-A9 MPCore ?
What is the purpose of DMAFLUSHP?
What is the purpose of WFI and WFE instructions and the event signals ?
What is the purpose of the Bypass Pixel Clock Divider field (BCD) in the Timing2 register?
What is the purpose of the DEBUG_LVL and TRACE_LVL configuration parameters?
What is the purpose of the PL022 IMSC, RIS, MIS and ICR registers?
What is the purpose of the PL330 DMAFLUSHP instruction?
What is the purpose of the RSTBYPASS input on the Cortex-R4?
What is the purpose of the Stick Parity Select (SPS) bit in the UART's LCR_H register?
What is the purpose of the ap_bit on PL340?
What is the purpose of the keyword 'LITE' in the ARMv7 Architecture Verification suite?
What is the relationship between HBURST and the PL081 DMAC Burst Size?
What is the relationship between the LOCZRAMA signal, ATCM and BTCM base addresses and TCM_HI_INIT_ADDR configuration option?
What is the significance of the CACHEID input with respect to the L2CC version?
What is the size/granularity of memory that I can select to be h/w coherent with CCI-400?
What is the speed grade of the LT-XC4V (Virtex-4) Logic Tile FPGA?
What is the state of the MMU at reset?
What is the state of the caches at reset?
What is the structure of the debug ROM tables in Cortex-M7 ?
What is the test procedure for ARM7EJ-S?
What is the test strategy for ARM soft cores?
What is the timing relationship between TDI/SDIN and TDO/SDOUTBS?
What is the total number of flip-flops in ARM7EJ-S?
What is the true interrupt latency of Cortex-M3 and Cortex-M4 for interrupt entry and exit?
What kind of bursts will the ARM966E-S perform?
What kind of unaligned AMBA access can Cortex-A7 generate ?
What might an initial configuration of the ARM7TDMI look like?
What might an initial configuration of the ARM9TDMI look like?
What restrictions does Eclipse impose on source file names?
What setup is needed to use DS-5 for debugging Android native (C/C++) applications and libraries?
What simulator/vector format options do I have with the ARM9 cores?
What size memory accesses does Model Debugger use?
What sort of system bus does the ARM7EJ-S have?
What state does MCLK need to be when nRESET is taken low?
What state is the ARM1176 in out of reset ?
What target hardware can I use RVDK for OKI with?
What texture formats are supported by OpenGL ES?
What tools are required to debug my Cortex-M3 with RVD/RVI?
What type of memory access does armcc use for different C constructs?
What values are in ARM registers after a power-on reset?
What values of HSIZE does the ARM946E-S use?
What version number should ARM968E-S have?
What version of the ARM development tools will an RVDS license enable?
What versions of the Java Runtime Environment are supported by the Eclipse plug-ins?
What will happen on a write-miss to a cacheable location?
What's the value of HBURST in PL081 when burst transfer request size = 4 (DBSize = 0b001)?
When DMA writes via ACP to coherent memory, does it pollute the L1 cache ?
When I compile an MDE application for the Mali FPGA board, I get compilation errors. What should I check for first?
When I try to set up Vector Catch on ISSM or RTSM models, I get an error message in RVD
When PL301 is rendered, why does it always include an APB slave interface?
When a master has issued a locked transfer with one ID can it start a different locked transfer with a different ID?
When an interconnect adds bits to the ID field does it add high-order bits or low-order bits?
When building in Ubuntu, CoAP tests do not continue and keep failing with a timeout
When can a master consider a write transaction complete, when it is trying to determine which write data sources it can interleave?
When connecting to a Cortex-M3 why do I see "Warning: 0x02190102: No access is provided to the register 'PRI_ISR'"?
When designing development boards what style JTAG connector should I use?
When does the ARM926EJ-S use its Write Buffer?
When is the SEVL instruction used?
When must the ABORT signal become active to signal a data abort or a prefetch abort?
When should I use adaptive clocking? Do I need to route RTCK to the JTAG connector?
When should I use the LVDS probe?
When should a master assert and deassert the HLOCK signal for a locked transfer?
When should a master deassert its HBUSREQ signal?
When there are several bursts with same ID to a slave, are they counted separately or as one in regard to the write data interleaving-depth of the slave?
When trying to run runDS-tc.sh, en error message 'Connection refused' is displayed
When using a synchronous clocking strategy the int_n and busy_n inputs have paths into the aclk domain. If a large delay is placed on the mclk signals these paths become untenable at high ACLK frequencies. Any workaround for this problem?
When will PL080 use the TransferSize value
When will the arbiter grant another master after a locked transfer?
When would LDRT instruction be used?
Where are $vector_catch and $semihosting_enabled in AXD?
Where are the built scripts (*.bat and *.sh) for the SystemC example?
Where can I buy RVDK for OKI?
Where can I find the driver for the HDLCD present on the V2P-CA15x2 and V2P-CA15x2-CA7x3 boards?
Where can I find details of the error and warning messages produced by the ADS build tools?
Where can I find details of the error and warning messages produced by the RVCT build tools?
Where can I find information on the versions of the ARM Architecture?
Where can I find pre-built Linux images for my Versatile Express system?
Where can I find the ARMv6 Architecture Reference Manual?
Where can I find the DSP instruction set of the ARM926EJ-S?
Where can I find the Eclipse extension point interface for adding third-party OS support in DS-5 Debugger?
Where can I find the latest Versatile Express DVD and how do I start up my Versatile Express system?
Where can I find the v6T2 (Thumb-2) Architecture Reference Manual?
Where can I get an ARMv8-A processor model?
Where can I get information on the ARM and Thumb Instruction Sets?
Where can I get support?
Where can I get the Cortex-M0 DesignStart processor IP?
Where can I obtain expansion connectors for the Evaluator-7T?
Where can I purchase an off-the-shelf ARM core?
Where can I purchase an off-the-shelf ARM-based processor?
Where do I find Debugger Internal Variables in RVD?
Where do I find the ARM FLEXlm License Management Guide documentation?
Where do I find the USB drivers for RVI-ME?
Where does DAPCLK come from?
Where in the JTAG scan chain should I connect my ETB?
Where is Application Note 72?
Where is the encryption key stored in a Logic Tile?
Where is the pin constraint file (UCF) for the LT-XC4V (Virtex-4) Logic Tile FPGA?
Where is the stack located by default on RealView profiler?
Where will an ARMv8-A processor start execution after reset?
Where will the ITCM be located at reset?
Which AHB-Lite BURST and TRANSFER types are produced by Cortex-M3 and Cortex-M4?
Which AN119 (Implementing AHB Peripherals in Virtex 2 Logic Tiles) image should I use?
Which AN152 (Using a CT11MPCore with the EB) FPGA, PLD and PDF versions should I use?
Which ARM compiler options should be used to generate NEON instructions from C/C++ code?
Which ARM cores does Multi-ICE support?
Which ARM cores does RVCT for BREW/BREW Builder support?
Which ARM cores support the embedded Configurable Operating System (eCoS)?
Which ARM processors are supported by DS-5?
Which ARM toolkit must I use to build Symbian OS/Apps?
Which ARM toolkits can be used to build BREW Apps?
Which ARM9EJ-S core should I use for ETM9 validation?
Which ARMv7-M Special Registers may be accessed by MSR/MRS instructions?
Which Application Notes work with which boards?
Which ETM signals should I connect to top-level ASIC pins?
Which Execution State (AArch) is the processor in?
Which GNU language extensions are supported by the ARM Compiler?
Which LT-XC4V (Virtex-4) Logic Tile schematic should I use?
Which XScale-based devices are supported by RVXDK?
Which architectures support the WFI instruction?
Which build tools are supported by the Fast Model Tools (System Generator)?
Which cached cores are available and what do they include?
Which core should I select when I am debugging the ARM1136J-S using RealView-ICE?
Which debuggers is RVI compatible with?
Which device can control the data transfer length, to or from a peripheral?
Which fault is caused by accessing a locked CoreSight register without unlocking it?
Which is the ETM used with Cortex-R4 microprocessor?
Which license features do I need to run a Virtual Platform (VP) or Exported Virtual Sub-system (EVS)?
Which license features do I need to run an RTSM (Real-Time System Model)?
Which pins of Cortex-M3 and Cortex-M4 can be excluded from toggle coverage?
Which schematic diagram should I use on the Versatile CD?
Which testbench should I use for ETM7 validation?
Which tools are required to synthesize the ARM7EJ-S?
Which validation tests should I run for my configuration?
Which vector table is used when an exception occurs in monitor mode?
Which version of the license server daemons should I run, and where do I find them?
Which versions of RVCT for BREW will my license file enable?
Which versions of RVD can I use with which versions of RVI?
Who gets to fill out a Customer Satisfaction survey?
Why after installing an ARM Compiler 5 patch does "armcc --vsn" report that my old build is still in use?
Why am I getting "ERROR: RVI not connected. Configure RVI" in the eXDI console after successfully configuring RVI using USB?
Why am I getting "armcc command with no effect" in Eclipse?
Why am I getting DENIED messages in my server log?
Why am I getting a FLEXlm -103,122 license error?
Why am I getting a FLEXlm -12,122 license error?
Why am I getting a FLEXlm -15 license error when using Parallel Make on Windows XP?
Why am I getting a FLEXlm -15 license error, even though my license server is running?
Why am I getting a FLEXlm -15,10 license error?
Why am I getting a FLEXnet -89 license error?
Why am I getting a FlexNet -7,10015 license error?
Why am I getting linker errors when building standalone assembly with MDK-ARM?
Why am I receiving the error message "Trace interface not initialised" when I try to use hardware profiling?
Why am I receiving the error message "Tracestream communication error"?
Why am I receiving the error message "Tracestream not supported" when I attempt to use hardware profiling?
Why am I seeing error and warning messages after I upgraded to RVD 4.1 or RVI 4.0?
Why am I unable to capture energy data using Streamline and Energy Probe on Red Hat Enterprise Linux 5?
Why am I unable to collect profiling data on the AB926 or PB926?
Why am I unable to connect to the ST-Ericsson U8500 platform after a reset?
Why are some DMA signals not used by the PL080?
Why are some Dynatext books not visible after installing/uninstalling other ARM products?
Why are the Evaluator-7T board registers not visible in RVD when using RealView ICE?
Why are the read and write address buses defined with all four bits of ACACHE. Does a read transaction need to give the write allocate information and vice versa?
Why can I not program my CT7TDMI with Progcards_RVI?
Why can I not run setuplinux.bin?
Why can I not see RealView ICE in the Connection Control Window?
Why can I not see my RVI over USB?
Why can I not set trace capture rules or load trace capture rules from a file?
Why can I not trace with a 4-bit or 8-bit data port width?
Why can I only see the core(s) in the RVD "Connect to Target" window when I have more components on my scan chain?
Why can MMU500 only configure SSDIndex 0-7?
Why can't I RELOAD once the traffic light and switch example is downloaded?
Why can't I add a custom device to the scan chain when using RVI 3.3?
Why can't I connect to my MultiTrace unit?
Why can't I export more than 8192 lines of trace from the RVD Analysis window?
Why can't I get the ARM720T TIC patterns to pass in my simulation?
Why can't I program the Logic Tile on my revision C PB926 + CT (AN125) platform?
Why can't I see a Profiler/tools directory containing armprocap in my RVDS install?
Why can't I single step or set breakpoints in RVD?
Why certain memory addresses are being accessed multiple times when using Load Multiple or Store Multiple instructions?
Why certain memory regions cannot be accessed in the Cortex-M3 Example System?
Why do "debug_tests" and "trace_tests" in CMSDK stall when using ARM GCC for compilation?
Why do ARM recommend a minimum of 12x difference between SSPCLK and SSPCLKIN in the slave?
Why do CodeWarrior and Eclipse insert additional command-line options?
Why do Cortex-A7 and Cortex-A15 behave differently when handling WFE instructions ?
Why do DTCM RAM blocks need to have the same wait state behavior?
Why do I get "Error code: LAUNCHER-11" when I start Eclipse/Workbench?
Why do I get a 'Configuration item not supported' warning in RVD?
Why do I get a 'Failed to Load the Kernel' error when connecting to my target?
Why do I get a compiler error when using the maximum negative number for a given type in an expression?
Why do I get a fault when I load a literal value and then branch to it?
Why do I get a single black line on my display when i change the resolution?
Why do I get errors from Make when trying to Build my application with RVD?
Why do I get the error "Flash Initialisation Failed" when booting my Versatile Express system?
Why do I have problems executing or stepping images in flash?
Why do I have problems using RVDv3.1 after applying a patch update?
Why do I not see component parameters in the System Generator canvas?
Why do I only see incorrect or corrupt trace being captured?
Why do I read FIQ GIC interrupt IDs in my IRQ handler?
Why do I receive errors when installing the RealView-ICE USB driver
Why do I see "Error: invalid absolute file" when I debug my CEVA DSP?
Why do I see "Warning: #1296-D: extended constant initialiser used"?
Why do I see "application configuration is incorrect" when loading an RTSM with Model Debugger?
Why do I see "license checkout" or "not supported" errors?
Why do I see "post connect" error when I try to connect to RVI-ME?
Why do I see C9931W or C9933W reported as an error?
Why do I see ETM FIFO overflow errors when using ETB trace capture mode in RVD?
Why do I see External Error: No Interface Initialized when trying to connect the Trace Analyser in RVD?
Why do I see no output in the trace capture window?
Why do I see the error message: 'sARMARMx_arm.exe - Entry Point Not Found'?
Why do I see the linker warning message L6221E?
Why do I see undefined reference to `SMSC_91C111_GetFactory()' when using SystemC export
Why do I see warning: 'Unknown EABI object attribute 34' when I link an ELF object generated by RVCT with the GNU linker?
Why do I sometimes see licensing error messages displaying the feature name "bsp_<feature>"?
Why do detailed tracepoints and triggers fail in Thumb code?
Why do different cores behave differently when executing a WFE instruction?
Why do some examples in RVDS 4.1 fail to build?
Why do some interrupts not work on CT11MPCore + EB?
Why do the "cname" headers (e.g., cmath) not include the "name.h" headers (e.g., math.h) within the global namespace?
Why do you supply both min and max Synopsys .lib files for a particular process corner?
Why does "RealView ICE Update" fail when I attempt to upgrade my RVI firmware?
Why does "armcc -E" preprocessing result in linker undefined symbol error?
Why does Eclipse rebuild all open projects when a new run is started?
Why does GDB show "Device is not selected" if UNKNOWN or non-ARM devices are present in the scanchain?
Why does Progcards detect the CT1156 as having an ARM1136JF-S core?
Why does Progcards detect the CT1176 as having an ARM1136JF-S core?
Why does Progcards fail to program PB11MPCore?
Why does Progcards fail to program the EB?
Why does Progcards_RVI fail to program large FPGA bitfiles?
Why does Progcards_RVI fail when downloading an FPGA image to the Logic Tile?
Why does RVD fail to connect to or step my SecurCore Target?
Why does RVD fail to program the first 256KB of NOR flash correctly on my PB926?
Why does RVD fail to set hardware breakpoints?
Why does RVD fail to start correctly with a TVS error message?
Why does RVD fail to write to same flash location twice?
Why does RVD provide Localhost (RVISS) and ISSM simulator connections?
Why does RVDS fail to install on a Windows machine configured as Turkish?
Why does RVIUpdate fail to update my RealView-ICE firmware?
Why does System Generator say "Cannot open include file: 'pv/PVBus.h' " when building?
Why does armlink treat libraries differently to objects?
Why does dependancy checking not reliably work for my Eclipse project?
Why does double-to-integer conversion give incorrect result?
Why does image load fail when writing to flash?
Why does malloc() get called when global C++ objects are initialised at startup?
Why does my ARM926EJ-S run slowly compared with an ARM7TDMI?
Why does my CT11MPCore have a red PCB?
Why does my Cortex-M processor Lock Up with a Hard Fault a few cycles after reset?
Why does my LVDS probe fail to work with RVI 3.4 and later? - Unprogrammed EEPROM devices
Why does my PB926 stop working when I attach a Logic Tile?
Why does my debugger fail to return ETM Trace data from Core Tiles on my Versatile baseboard?
Why does my debugger fail to return ETM Trace from the PB926 and AB926?
Why does my unaliged LDR/STR abort?
Why does progcards_rvi report an error after I try to connect to my RVI?
Why does semi hosting fail with specific bit patterns at the SVC vector?
Why does syntax highlighting not work for assembler files?
Why does the 'Synchronised' trace view only allow me to synchronise trace output with the disassembly window and not the source window?
Why does the ARMulator Timer Peripheral fail to work for ARM11 RVISS targets?
Why does the BCD file for Integrator/CP produce lots of errors?
Why does the Cortex-M3 TRM imply that Cortex-M3 can fetch from Peripheral and External Device memory?
Why does the DSM CPSR contain X values after changing nIRQ/nFIQ inputs?
Why does the LCD have random pixels?
Why does the NFU utility not work on EB RevC boards?
Why does the connection progress bar get stuck when I launch an RTSM or a FVP model (with Linux) connection?
Why does the connection script fail to run
Why does the core pipeline have 2 fetch stages ?
Why does the debugger report "Hardware interface timeout"?
Why does the installer/uninstaller repeatedly insist I reboot my machine?
Why does the linker select weak definitions instead of non-weak ones from a library?
Why does the processor enter standby when using WFE instruction but not when using WFI instruction ?
Why doesn't my AXI peripheral work?
Why doesn't my new DSTREAM unit work with RVD ?
Why doesn't my revision D EB work?
Why doesn't the UART0 serial port work on my revision E PB926?
Why has my development tool hardware stopped working?
Why have memory types been defined in the ARM V6 ISA ?
Why is "u-boot" not present in the Versatile Express DVD deliverables?
Why is AXI spec suitable for "high bandwidth" designs ?
Why is DS-5 unable to control my target when debugging the Linux kernel via JTAG?
Why is RealView-ICE v1.5 firmware no longer available for download?
Why is UniqueClean an illegal end state for WriteUnique and WriteLineUnique transactions?
Why is data corrupted on RD/WR transactions to DDR memory on the V2P-CA15-A7 board?
Why is my cramfs root filesystem mount (/dev/mtdblock0) failing on the Versatile Express platform when running v2.6.35 and later Linux kernels?
Why is my target not responding to debug commands after connection with RVD?
Why is no .rpa file generated when I profile my custom RTSM?
Why is the "T" bit 0 when I load my program to a Cortex-M0 or Cortex-M3 processor?
Why is the ARM720's Dhrystone MIPS rating lower than that of the ARM7TDMI?
Why is the EEPROM on my V2F-1XV5 RevC programmed as RevB?
Why is the Flash Memory on the on the static memory expansion board not working?
Why is the MMU implemented in 2 levels? What is the need for a DTE and PTE in the MMU implementation?
Why is the READY signal not sticky?
Why is the SysTick Calibration TENMS value one less than the number of clock cycles required for 10ms?
Why is the VALID signal described as "sticky"?
Why is the VALID signal sticky?
Why is there ACLK and ACLKEN on the ARM1176 ?
Why is there a 1KB restriction in AHB?
Why is trace bandwidth so limited on PB-A8?
Why might RVDS 4.0 fail to install?
Why might images built on different platforms be slightly different?
Why might the +FIRST and +LAST scatter-loading attributes not behave as you might expect?
Why must I enable the MMU to use the D-Cache but not for the I-Cache?
Why must the chip designer release "PORESETn" synchronously to FCLK?
Why should I only use NSC regions for secure gateway veneers?
Why should you care about the nIRQ/nFIQ and nIRQOUT/nFIQOUT signals toggling when there are GICC_IAR reads?
Why the simulation stalls when printf() is used in my C code?
Why would RVD/DS-5 not connect to my i.MX-based target when running Linux ?
Will Mali-400 MP ever generate leading write data before the write address for an AXI transaction?
Will a reset cause the buffers to drain?
Will boards from the older Versatile range work with the new Versatile Express family of boards?
Will the ARM946E-S generate INCR bursts?
Windows cannot find 'c:\windows\system32\telnet.exe'
Windows installation fails when using substituted path
Windows98 cannot reboot after installing RVDK for OKI
Workbench or RVD launching problems caused by unicode characters in username
Writing interrupt handlers for v6/v7 cores
X2 FEATURE OF ATMEL DEVICES
XC16X OCDS INTERFACE DOES NOT WORK
XC800 SSC DIALOG DISPLAY INCOMPLETE
XC800: 'Use multiple DPTR registers' may cause runtime errors
XDATA BANKING WITH R8051XC
XDATA OVERLAYING
XDATA PROBLEMS PORTING C51 CODE TO C251
XOR GIVES INCORRECT RESULTS
XSMALL DIRECTIVE
XTINY DIRECTIVE
XWORD MACRO QUESTIONS
Y2K COMPLIANCE
_CHKFLOAT_ RETURNS STRANGE VALUES
_CHKFLOAT_ RETURNS STRANGE VALUES
_GETKEY DOESN'T WORK WITH MON51
_INIT_BOXH LIBRARY ROUTINE
_POP_ INTRINSIC LIBRARY ROUTINE
_PRIORD_ INTRINSIC LIBRARY ROUTINE
_PRIOR_ INTRINSIC LIBRARY ROUTINE
_PUSH_ INTRINSIC LIBRARY ROUTINE
_TESTBIT_ FUNCTION GIVES A WARNING
_TESTCLEAR_ INTRINSIC FUNCTION
__DATE__ AND __TIME__ MACROS
__ERROR__ DIRECTIVE
__INLINE GENERATES CALL OR WARNING #197
armlink/fromelf: Merging load regions to obtain a single binary output
rm_ExceptionDuringProcessing() does not return properly to Thumb
uVISION: C:\Keil\Tools.ini does not contain a valid tool path
ARM architecture
Reference Manuals
ARMv8.1-M Reference Manual
Arm®v8-M Architecture Reference Manual Reference Manual
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ArmARM v8-A Supplement - MPAM (Issue A.a)
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ArmARM v8-A Supplement - SVE (Issue A.e)
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ArmARM v8-A Supplement - RAS (Issue C.a)
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ARMv8-A Reference Manual
ARMv8-A Reference Manual (Issue D.a)
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ARMv8-M Reference Manual
Arm® v8-M Architecture Reference Manual Reference Manual
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ARMv7-M Reference Manual
ARM®v7-M Architecture Reference Manual Reference Manual
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ARMv6-M Reference Manual
ARM®v6-M Architecture Reference Manual Reference Manual
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ARMv7-AR Reference Manual
ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
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ARMv5 Reference Manual
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Instruction Set Quick Reference Cards
ARM and Thumb-2 Instruction Set Quick Reference Card
PDF version
Thumb 16-bit Instruction Set Quick Reference Card
PDF version
Vector Floating Point Instruction Set Quick Reference Card
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System Architecture
Trusted Base System Architecture Client
TRUSTED BASE SYSTEM ARCHITECTURE CLIENT (4TH EDITION) System Hardware on ARM®
PDF version
Power Control Framework
Arm® Power Policy Unit Architecture Specification
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ARM® System Control and Management Interface Platform Design Document
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Software Delegated Exception Interface (SDEI) Platform Design Document
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ARM® Management Mode Interface Specification
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ACPI Companion Specs
ARM Functional Fixed Hardware Specification (FFH)
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IO Remapping Table Platform Design Document
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Arm® Server Base System Architecture 5.0 Platform Design Document (SBSA)
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Arm® Server Base Boot Requirements 1.1 Platform Design Document (SBBR)
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ARM® Power State Coordination Interface Platform Design Document
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ARM Architecture Standard Configurations System Software on ARM Processors
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Principles of ARM Memory Maps White Paper
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SMC CALLING CONVENTION System Software on ARM® Platforms
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ARM Debug and Trace, Configuration and Usage Models Platform Design Document
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Jazelle
Jazelle v1 Architecture Reference Manual
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CoreSight and ETM Architecture Specifications
Embedded Trace Router Architecture (ETR) Specification
Arm® Embedded Trace Router Architecture Specification
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Arm Debug Interface Architecture Specification ADIv6.0
Arm® Debug Interface Architecture Specification ADIv6.0 Architecture Specification
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Advanced Communications Channel
Advanced Communications Channel Architecture Specification
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ARM System Trace Macrocell Programmers’ Model Architecture Specification V1.1 Architecture Specification
PDF version
CoreSight Program Flow Trace Architecture Specification
Preface
About this specification
Product revision status
Intended audience
Using this specification
Conventions
Typographical
Numbering
Further reading
ARM publications
Feedback
Feedback on the Program Flow Trace architecture
Feedback on this specification
Introduction
About the Program Trace Macrocell
Structure of a PTM
The debug environment
Thumb, ThumbEE, and Java support
Connections to a PTM
Trace compression
Resets
Program Flow Tracing
About Program Flow Tracing
Tracing branches
Tracing exceptions
Nonwaypoint instructions
PFT trace example
Waypoint instructions
Unpredictable encodings
Upgrading a nonwaypoint instruction on an exception
Timestamping
Virtualization
Program Trace Macrocell Programmers Model
About the PTM programmers model
CoreSight support
Programmers model requirements
Topology detection requirements
TraceEnable
About TraceEnable
Imprecise TraceEnable events
TraceEnable rules
The TraceEnable start/stop block
TraceEnable Include/exclude control
Address comparators
General behavior of address comparators
Terms used to describe address comparator behavior
Single address comparators (SACs)
Address range comparators (ARCs)
Context ID comparators
Virtual Machine ID comparator
EmbeddedICE watchpoint comparator inputs
EmbeddedICE watchpoint comparator input behavior
Default behavior of EmbeddedICE watchpoint comparator inputs
Pulse and latch behavior of EmbeddedICE watchpoint comparator inputs
Examples of using EmbeddedICE watchpoint comparator inputs
Event resources and PTM events
The PTM event resources
Example PTM resource configuration
Defining a PTM event
Read values of event registers
Examples of event programming
Summary of the PTM events
PTM counters
Use of PTM counters
The PTM sequencer
Use of the PTM sequencer
Instrumentation resources
The Instrumentation resource event resources
Instructions for controlling the Instrumentation resources
Hint field encodings for the DBG Instrumentation instructions
Instrumentation resource behavior when tracing parallel execution
PTM input resources
External inputs
Extended external inputs
Non-secure state resource
Trace prohibited resource
Hard-wired TRUE resource
PTM external outputs
Triggering a trace run
About the PTM registers
Register short names
PTM trace and PTM management registers
Accessing the PTM registers
Coprocessor access
The coprocessor access model
Determination of support
Behavior of other CP14 accesses with Opcode_1 equal to 1
Memory-mapped access
Restrictions on the type of access to PTM registers
PTM register access models
Use of the Programming bit
Programming bit and associated state
PTM state items
Synchronization of PTM register updates
Organization of the PTM registers
PTM register descriptions
Main Control Register, ETMCR
Checking support for implementation defined features
Configuration Code Register, ETMCCR
Trigger Event Register, ETMTRIGGER
Status Register, ETMSR
System Configuration Register, ETMSCR
About the TraceEnable control registers
TraceEnable Start/Stop Control Register, ETMTSSCR
TraceEnable Event Register, ETMTEEVR
TraceEnable Control Register, ETMTECR1
Tracing all memory
FIFOFULL Level Register, ETMFFLR
About the address comparator registers
Address Comparator Value Registers, ETMACVRn
Address Comparator Access Type Registers, ETMACTRn
Filtering by state and mode, from PFTv1.1
Access types for address range comparators
Selecting a range to include address 0xFFFFFFFF
About the counter registers
Reduced function counter, from PFTv1.1
Counter Reload Value Registers, ETMCNTRLDVRn
Counter Enable Event Registers, ETMCNTENRn
Counter Reload Event Registers, ETMCNTRLDEVRn
Counter Value Registers, ETMCNTVRn
About the sequencer registers
Sequencer State Transition Event Registers, ETMSQabEVR
Current Sequencer State Register, ETMSQR
External Output Event Registers, ETMEXTOUTEVRn
About the Context ID comparator registers
Context ID Comparator Value Registers, ETMCIDCVRn
Context ID Comparator Mask Register, ETMCIDCMR
Implementation specific registers, ETMIMPSPEC0 to ETMIMPSPEC7
Implementation specific Register 0
Synchronization Frequency Register, ETMSYNCFR
ID Register, ETMIDR
Configuration Code Extension Register, ETMCCER
Extended External Input Selection Register, ETMEXTINSELR
TraceEnable Start/Stop EmbeddedICE Control Register, ETMTESSEICR
EmbeddedICE Behavior Control Register, ETMEIBCR
Timestamp Event Register, ETMTSEVR
Auxiliary Control Register, ETMAUXCR
CoreSight Trace ID Register, ETMTRACEIDR
VMID Comparator Value Register, ETMVMIDCVR
About the Operating System Save and Restore registers
OS Lock Access Register, ETMOSLAR
OS Lock Status Register, ETMOSLSR
OS Save and Restore Register, ETMOSSRR
Device Power-Down Control Register, ETMPDCR
Device Power-Down Status Register, ETMPDSR
Integration Mode Control Register, ETMITCTRL
About the claim tag registers
Claim Tag Set Register, ETMCLAIMSET
Claim Tag Clear Register, ETMCLAIMCLR
About the lock registers
Lock Access Register, ETMLAR
Lock Status Register, ETMLSR
Authentication Status Register, ETMAUTHSTATUS
Implementation of the Secure non-invasive debug field
Device Configuration Register, ETMDEVID
Device Type Register, ETMDEVTYPE
About the Peripheral Identification Registers
Peripheral ID0 Register, ETMPIDR0
Peripheral ID1 Register, ETMPIDR1
Peripheral ID2 Register, ETMPIDR2
Peripheral ID3 Register, ETMPIDR3
Peripheral ID4 Register, ETMPIDR4
Peripheral ID5 to Peripheral ID7 Registers, ETMPIDR5 to ETMPIDR7
About the Component Identification Registers
Component ID0 Register, ETMCIDR0
Component ID1 Register, ETMCIDR1
Component ID2 Register, ETMCIDR2
Component ID3 Register, ETMCIDR3
Power-down support
Power down support in PFTv1.0
SinglePower in PFTv1.0
Full Power Down Support in PFTv1.0
Power down support from PFTv1.1
SinglePower from PFTv1.1
Full Power Down Support from PFTv1.1
Significant changes to power down support introduced in PFTv1.1
PTM behavior when the OS Lock is set
Guidelines for the PTM trace registers to be saved and restored
About the access permissions for PTM registers
Access types
Meanings of terms and abbreviations used in this section
Restrictions on accesses using a Direct JTAG connection
Effect of DBGSWENABLE on register access
Access permissions for PFTv1.0 SinglePower implementations
PTM state definitions, PFTv1.0 SinglePower implementations
Debugger accesses, PFTv1.0 SinglePower implementations
Memory-mapped accesses, PFTv1.0 SinglePower implementations
Coprocessor accesses, PFTv1.0 SinglePower implementations
Access permissions for PFTv1.0 with multiple power implementations
PTM state definitions, PFTv1.0 with multiple power implementations
Debugger accesses, PFTv1.0 with multiple power implementations
Memory-mapped accesses, PFTv1.0 with multiple power implementations
Coprocessor accesses, PFTv1.0 with multiple power implementations
Access permissions for PFTv1.1 SinglePower implementations
PTM state definitions, PFTv1.1 SinglePower implementations
Debugger accesses, PFTv1.1 SinglePower implementations
Memory-mapped accesses, PFTv1.1 SinglePower implementations
Coprocessor accesses, PFTv1.1 SinglePower implementations
Access permissions for PFTv1.1 with multiple power implementations
PTM state definitions, PFTv1.1 with multiple power implementations
Debugger accesses, PFTv1.1 with multiple power implementations
Memory-mapped accesses, PFTv1.1 with multiple power implementations
Coprocessor accesses, PFTv1.1 with multiple power implementations
Programming the PTM to trace all execution
Program Flow Trace Protocol
About the Program Flow Trace protocol
PFT atoms
Summary of PFT packets
Cycle-accurate tracing
PFT packet formats
A-sync, alignment synchronization packet
I-sync, instruction synchronization packet
The I-sync cycle count field
Periodic and Nonperiodic I-sync packets
Atom packet
Atom packets when cycle-accurate tracing is not enabled
Atom packets when cycle-accurate tracing is enabled
Branch address packet
Branch address packet cycle count information in cycle-accurate mode
Address and cycle count compression in branch address packets
Address compression
Branches to Thumb or ThumbEE state, without exception information byte
Branches to Thumb or ThumbEE state, with exception information byte
Branches to ARM state, without exception information byte
Branches to ARM state, with exception information byte
Cycle count compression
Waypoint update packet
Trigger packet
Context ID packet
VMID packets
Timestamp packet
Encoding of the timestamp value
Exception return packet
Ignore packet
Branch broadcasting
Prohibited regions
Behavior of the PTM when the processor is in a prohibited region
Non-invasive debug disabled
Trace FIFO overflow
Wait for Interrupt and Wait for Event
Large blocks of instructions
Synchronization
Periodic synchronization
Forced overflow
Alignment synchronization
Instruction synchronization
Nonperiodic I-sync
Periodic I-sync
Timestamp synchronization
Tracing security state changes
Changing from Non-secure to Secure state
Changing from Secure to Non-secure state
Use of a return stack
Timestamping
Trace flushing
CoreSight or other ATB flush request
Setting the Programming bit or the OS Lock
WFI or WFE request
Tracing Thumb instructions
32-bit Thumb instructions
Thumb CBZ and CBNZ instructions
Jazelle state
Debug state
Tracing Exceptions
About exception tracing in the PFT architecture
The different exception cases
Exception occurs after a nonwaypoint instruction
Exception occurs immediately after a waypoint instruction
Exception occurs immediately after another exception
Exceptions occurring close together but not back-to-back
Turning trace on between two back-to-back exceptions
Exception occurs immediately after trace turn-on
Exception occurs before execution of instruction at the I-sync target address
Exception occurs after execution of instruction at the I-sync target address
Tracing the different exception types
Processor reset exception
Undefined Instruction exception
SVC (Supervisor Call) or SMC (Secure Monitor Call) exception
Prefetch Abort exception
Synchronous Data Abort exception
Asynchronous Data Abort, FIQ or IRQ exception
Entry to Hyp mode
Debug state entry, when Halting debug-mode is enabled
Tracing exit from Debug state
ThumbEE check that goes to a handler, including the CHKA instruction
Jazelle exception that goes to an ARM or Thumb state handler
Secure to Non-secure state change
Other exceptions
Waypoint update addresses
PTM Quick Reference Information
PTM event resources
Resource identification and event encoding
Resource control registers
Summary of implementation defined PTM features
Trace Decompressor Operation
About PTM trace decompression
PFT trace state and objects
PFT state information
PFT output objects
PFT trace decompression flow
Overall PFT trace decompression flow
Details of PFT trace decompression operations
branch_no_excp()
branch_with_excp()
analyze_atomheader()
analyze_cid()
analyze_vmid()
analyze_waypoint_update()
analyze_eret()
decode_instr()
Software Issues for PFT
About tracing dynamically-loaded code
Simple overlay support
Software support for Context ID
Hardware support for Context ID
Architecture Version Information
PFTv1.0 to PFTv1.1
Programmers model
Signal protocol
Glossary
ARM® CoreSight™ Architecture Specification Architecture Specification
PDF version
Embedded Trace Macrocell (ETMv4) Architecture Specification
Documentation placeholder
Embedded Trace Macrocell (ETMv3) Architecture Specification
Preface
About this specification
Product revision status
Intended audience
Using this specification
Conventions
Typographic conventions
Signals
Numbers
Additional reading
The ETM documentation suite
Other ARM publications
Feedback
Feedback on this specification
Introduction
About Embedded Trace Macrocells
Structure of an ETM
The debug environment
Thumb and Java support
Trace compression
ETM versions and variants
Controlling Tracing
About controlling tracing
ETM event resources
Memory access resources
Single address comparators
Address range comparators
No data address comparator option, ETMv3.3 and later
Data value comparators
Context ID comparators
Virtual Machine ID comparator
EmbeddedICE watchpoint comparators
Memory map decoder (MMD)
Instrumentation resources, ETMv3.3 and later
Derived resources
Counters
Sequencer
Trace start/stop resource
External inputs
Hard-wired input
External inputs
Extended external input selectors
Non-secure state resource
Prohibited region resource
Example resource configuration
ETM event logic
Triggering a trace run
External outputs
Trace filtering
Definitions of when an ETM is tracing
Behavior while tracing is prohibited
Programming strategies
TraceEnable and filtering the instruction trace
Data-controlled instruction tracing
Imprecise TraceEnable events
Rules for the transition of TraceEnable
The trace start/stop block
Using the trace start/stop block to control TraceEnable
ViewData and filtering the data trace
Imprecise ViewData events
Setting start and stop conditions
Filter Coprocessor Register Transfers (CPRT) in ETMv3.0 and later
Operation of ViewData
ViewData operation examples for Exclude mode
ViewData operation examples for Mixed mode
Restrictions on ViewData programming
Preventing FIFO overflow
Processor stalling, FIFOFULL
Data suppression
Address comparators
Comparator access size
Comparator access size field behavior, in ETMv3.1 and later
Single address comparators configured for data addresses
Single address comparators configured for instruction addresses
Address range comparators configured for data addresses
Address range comparators configured for instruction addresses
Comparator access size field behavior, in ETMv3.0 and earlier
Address range comparison behavior, in ETMv3.0 and earlier
Exact matching, in ETMv2.0 and later
Exact matching for instruction address comparisons
Exact matching for data address comparisons
Additional details of the effect of the Exact match bit
Exact matching, in ETMv1.x
Behavior of address comparators
Access types for address range comparators
Selecting a range to include address 0xFFFFFFFF
Comparator precision
Coprocessor transfers
Comparator configuration example
Operation of the comparators
Programming the comparator registers for this example
Operation of data value comparators
Terms used in this section
Operation of data value comparators, in ETMv3.2 and earlier
Operation of data value comparators, in ETMv3.3 and later
Data value matching with single address comparators
Constraints and rules for data value matching with single address comparators
Data value matching with address range comparators
Address matching of an address range comparator
Data value matching of an address range comparator
Constraints and rules for data value matching with address range comparators
Summary of alignment and endianness considerations for different ETM versions
Instrumentation resources, from ETMv3.3
The Instrumentation resource event resources
Instructions for controlling the Instrumentation resources
Hint field encodings for the DBG instrumentation instructions
Instrumentation resource behavior when tracing parallel execution
Trace port clocking modes
ETMv1 and ETMv2 behavior
ETMv3 behavior
Considerations for advanced processors, ETMv2 and later only
Parallel execution
Rules for parallel execution
Independent load/store unit
Consequences of parallel execution on counters
Consequences of parallel execution on the sequencer
Supported standard configurations in ETMv1
Choosing a configuration
ETM7 supported configurations
ETM9 supported configurations
Supported configurations from ETMv2
Behavior when non-invasive debug is disabled
Programmers’ Model
About the programmers’ model
Programming and reading ETM registers
Direct JTAG access
Restricting Direct JTAG access
Coprocessor access, ETMv3.1 and later
Coprocessor models
Limited register set model, ETMv3.1 and ETMv3.2 only
Full access model, ETMv3.3 and later
Behavior of coprocessor accesses
Restricting coprocessor access
Determination of support
Behavior of other CP14 accesses with Opcode_1 equal to 1
ETMv3.1 and v3.2
ETMv3.3 and later
Memory-mapped access, ETMv3.2 and later
Restrictions on the type of access to ETM registers
ETM register access models
Synchronization of ETM register updates
CoreSight support
Programmers’ model requirements
Topology detection requirements
The ETM registers
ETM Trace and ETM Management registers, from ETMv3.3
Reset behavior
Use of the Programming bit
ETM Programming bit and associated state
ETM state items
ETMv3.0 and earlier
ETMv3.1 and later
Detailed register descriptions
Main Control Register, ETMCR
Additional information on the ETMCR
ETM port size encoding
Restrictions on the use of the ETMEN signal
Checking for implementation defined features, from ETMv3.3
Checking whether data suppression is supported, in ETMv3.3 and later
Restriction if FIFOFULL and data suppression are both implemented
Checking support for cycle-accurate tracing, ETMv3.3 and later
Checking available data tracing options, ETMv3.3 and later
Configuration Code Register, ETMCCR
Trigger Event Register, ETMTRIGGER
ASIC Control Register, ETMASICCR
ETM Status Register, ETMSR, ETMv1.1 and later
System Configuration Register, ETMSCR, ETMv1.2 and later
About the TraceEnable registers
Tracing all memory
TraceEnable Start/Stop Control Register, ETMTSSCR, ETMv1.2 and later
TraceEnable Control 2 Register, ETMTECR2, ETMv1.2 and later
TraceEnable Event Register, ETMTEEVR
TraceEnable Control 1 Register, ETMTECR1
Controlling FIFO overflow using the FIFOFULL registers
FIFOFULL Region Register, ETMFFRR
FIFOFULL Level Register, ETMFFLR
About the ViewData registers
Enabling ViewData throughout memory
ViewData Event Register, ETMVDEVR
ViewData Control 1 Register, ETMVDCR1
ViewData Control 2 Register, ETMVDCR2
ViewData Control 3 Register, ETMVDCR3
About the address comparator registers
Address Comparator Value Registers, ETMACVRn
Address Comparator Access Type Registers, ETMACTRn
Filtering by state and mode, in ETMv3.5
Access types for address range comparators
Selecting a range to include address 0xFFFFFFFF
About the data value comparator registers
Alignment considerations
Associating data value comparators with address comparators
Data Comparator Value Registers, ETMDCVRn
Data Comparator Mask Registers, ETMDCMRn
About the counter registers
Reduced function counter, ETMv3.5
Counter Reload Value Registers, ETMCNTRLDVRn
Counter Enable Registers, ETMCNTENRn
Counter Reload Event Registers, ETMCNTRLDEVRn
Counter Value Registers, ETMCNTVRn
About the sequencer registers
Sequencer State Transition Event Registers, ETMSQabEVR
Current Sequencer State Register, ETMSQR
External Output Event Registers, ETMEXTOUTEVRn
About the Context ID comparator registers, ETMv2.0 and later
Context ID Comparator Value Registers, ETMCIDCVRn
Context ID Comparator Mask Register, ETMCIDCMR
Implementation specific registers
Implementation specific Register 0
Synchronization Frequency Register, ETMSYNCFR, ETMv2.0 and later
Finding the access type, ETMv3.4 and later
ID Register, ETMIDR, ETMv2.0 and later
The ETM architecture version
The Processor family field
Implementation revision
Configuration Code Extension Register, ETMCCER, ETMv3.1 and later
Extended External Input Selection Register, ETMEXTINSELR, ETMv3.1 and later
TraceEnable Start/Stop EmbeddedICE Control Register, ETMTESSEICR, ETMv3.4
EmbeddedICE Behavior Control Register, ETMEIBCR, ETMv3.4 and later
Timestamp Event Register, ETMTSEVR, ETMv3.5
Auxiliary Control Register, ETMAUXCR, ETMv3.5
CoreSight Trace ID Register, ETMTRACEIDR, ETMv3.2 and later
VMID Comparator Value Register, ETMVMIDCVR, ETMv3.5
ETM ID Register 2, ETMIDR2, ETMv3.5
About the Operating System Save and Restore Registers, ETMv3.3 and later
OS Lock Access Register, ETMOSLAR, ETMv3.3 and later
OS Lock Status Register, ETMOSLSR, ETMv3.3 and later
OS Save and Restore Register, ETMOSSRR, ETMv3.3 and later
Device Power-Down Status Register, ETMPDSR, ETMv3.3 and later
Power Down Control Register, ETMPDCR, ETMv3.5
Integration Mode Control Register, ETMITCTRL, ETMv3.2 and later
About the claim tag registers, ETMv3.2 and later
Claim Tag Set Register, ETMCLAIMSET
Claim Tag Clear Register, ETMCLAIMCLR
About the lock registers, ETMv3.2 and later
Lock Access Register, ETMLAR, ETMv3.2 and later
Lock Status Register, ETMLSR, ETMv3.2 and later
Authentication Status Register, ETMAUTHSTATUS, ETMv3.2 and later
Implementation of the Secure non-invasive debug field
CoreSight Device Configuration Register, ETMDEVID, ETMv3.2 and later
CoreSight Device Type Register, ETMDEVTYPE, ETMv3.2 and later
About the CoreSight Peripheral Identification Registers, ETMv3.2 and later
Peripheral ID0 Register, ETMPIDR0
Peripheral ID1 Register, ETMPIDR1
Peripheral ID2 Register, ETMPIDR2
Peripheral ID3 Register, ETMPIDR3
Peripheral ID4 Register, ETMPIDR4
Peripheral ID5 to Peripheral ID7 Registers, ETMPIDR5 to ETMPIDR7
About the CoreSight component identification registers, ETMv3.2 and later
Component ID0 Register, ETMCIDR0
Component ID1 Register, ETMCIDR1
Component ID2 Register, ETMCIDR2
Component ID3 Register, ETMCIDR3
Using ETM event resources
Resource identification
Resource encoding
Boolean combinations for defining events
Where events are used
Defining events
Examples of event and resource programming
Example ViewData and TraceEnable configurations
An example ViewData configuration
An example TraceEnable configuration
Power Down support
Power down support in ETMv3.3 and ETMv3.4
SinglePower in ETMv3.3 and ETMv3.4
Full Power Down Support in ETMv3.3 and ETMv3.4
Power down support in ETMv3.5
SinglePower in ETMv3.5
Full Power Down Support in ETMv3.5
Significant changes to power down support introduced in ETMv3.5
ETM behavior when the OS Lock is set
Guidelines for the ETM trace registers to be saved and restored
About the access permissions for ETM registers
Access types
Meanings of terms and abbreviations used in this section
Restrictions on accesses using a Direct JTAG connection
Effect of DBGSWENABLE on register access
Access permissions for ETMv3.3 and ETMv3.4, SinglePower
ETM state definitions, ETMv3.3 and ETMv3.4, SinglePower
Debugger accesses, ETMv3.3 and ETMv3.4, SinglePower
Memory-mapped accesses, ETMv3.3 and ETMv3.4, SinglePower
Coprocessor accesses, ETMv3.3 and ETMv3.4, SinglePower
Access permissions for ETMv3.3 and ETMv3.4, multiple power domains
ETM state definitions, ETMv3.3 and ETMv3.4, multiple power domains
Debugger accesses, ETMv3.3 and ETMv3.4, multiple power domains
Memory-mapped accesses, ETMv3.3 and ETMv3.4, multiple power domains
Coprocessor accesses, ETMv3.3 and ETMv3.4, multiple power domains
Access permissions for ETMv3.5, SinglePower
ETM state definitions, ETMv3.5, SinglePower
Debugger accesses, ETMv3.5, SinglePower
Memory-mapped accesses, ETMv3.5, SinglePower
Coprocessor accesses, ETMv3.5, SinglePower
Access permissions for ETMv3.5, multiple power domains
ETM state definitions, ETMv3.5, multiple power domains
Debugger accesses, ETMv3.5, multiple power domains
Memory-mapped accesses, ETMv3.5, multiple power domains
Coprocessor accesses, ETMv3.5, multiple power domains
Signal Protocol Overview
About trace information
Signal protocol variants
Structure of the trace port
Signals
ETMv1.x and ETMv2.x signals
ETMv3.x signals
Multiplexed trace port (ETMv1.x and ETMv2.x only)
Demultiplexed trace port (ETMv1.x and ETMv2.x only)
ETM structures
ETMv1.x
ETMv2.x
ETMv3.x
Decoding required by trace capture devices
Trigger conditions
Trace disabled conditions
Storage of TRACECTL
Instruction trace
Instruction trace filtering
Direct and indirect branches
Exceptions
Jazelle and ThumbEE exceptions
32-bit Thumb instructions
Thumb CBZ and CBNZ instructions
Data trace
Data access filtering
Address and data selection
Preloads
Asynchronous data aborts
Context ID tracing
Debug state
Endian effects and unaligned access
Summary of ARM behavior
Representation of data in the trace
Definitions
Load/Store Multiple (LSM) instructions
Data Instructions
Direct branch instructions
Exception return instructions
Coprocessor operations
Coprocessor data operation
Coprocessor data transfer
ETMv1
Coprocessor register transfer
Wait For Interrupt and Wait For Event
ETMv1 Signal Protocol
ETMv1 pipeline status signals
Trigger PIPESTAT signals
ETMv1 trace packets
Rules for generating and analyzing the trace in ETMv1
Additional considerations for 16-bit ports
Example ETMv1 trace
Pipeline status and trace packet association in ETMv1
Instruction tracing in ETMv1
Direct branches to the exception vector table
ARM and Thumb code
Java code
Compressed branch address packet structure
Moving to and from Jazelle state (ETMv1.3 only)
Branch reason codes
Trace synchronization in ETMv1
Address Packet Offset
Full address output
Context ID tracing
Data tracing in ETMv1
PIPESTAT signals indicating data accesses in the pipeline
Load/Store Multiple instructions
Trace packet sequence for data accesses
Data aborts
Address compression performed by the ETM
Filtering the ETMv1 trace
Enabling trace
Disabling trace
Data accesses during disabled trace
Precise events
FIFO overflow
System stalling
Cycle-accurate tracing
Tracing Java code, ETMv1.3 only
ETMv2 Signal Protocol
ETMv2 pipeline status signals
Wait PIPESTAT signals
Branch phantom PIPESTAT signals
Data PIPESTAT signals
Instruction Executed PIPESTAT signals
Instruction Not Executed PIPESTAT signals
TD PIPESTAT signals
Trigger PIPESTAT signals
ETMv2 trace packets
Rules for generating and analyzing the trace in ETMv2
Trace packet types
Trace packet headers
Normal Data packets
64-bit data transfers
Load Miss packets
Load Miss Occurred
Load Miss Data
Out-of-order miss data
Rules for generation of Load Miss trace packets
64-bit loads
Value Not Traced packets
Context ID packets
Trace synchronization in ETMv2
Trace FIFO offsets
TFO values
TFO formula
General TFO packet structure
Trigger considerations
Mid-byte TFO outputs
TFO packet types
TFO packet headers
Normal TFO packets
TFO reason codes
LSM In Progress TFO packets
Data address synchronization
Context ID tracing
Tracing through regions with no code image
Instruction tracing with ETMv2
Branch Address trace packets
Branch address generation
Exception branch addresses
Full branch address reason codes
Data tracing in ETMv2
Data aborts
Imprecise data aborts, ETMv2.1 and later
Decoding the data trace packets
Address compression performed by the ETM
Filtering the ETMv2 trace
Enabling trace
Disabling trace
Data accesses during disabled trace
FIFO overflow
Cycle-accurate tracing
ETMv3 Signal Protocol
Introduction
Packet types
Instruction tracing
P-headers
Generation
P-header encodings in non cycle-accurate mode
P-header encodings in cycle-accurate mode
The cycle-accurate mode format 4 P-header, ETMv3.3 and later
Condition codes on canceled and undefined instructions
Cycle information, for cycle-accurate tracing
Cycle count packet
Branch Packets
Branch packet summary
Branch packet formats with the original address encoding scheme
Branch packet formats with the alternative address encoding scheme
Branch packets without Exception Information Bytes, in the alternative encoding
Branch packets with Exception Information Bytes, in the alternative encoding
Exception Information Bytes
Encoding of Exception[8:0], for ARMv7-M processor architectures
Encoding of Exception[3:0], for processor architectures other than ARMv7-M
Possible combinations of Excp[8:0], Can and Resume[3:0]
Extended Exception handling in Instruction-only trace
The AltISA bit, ETMv3.3 and later
Branch address packets for change of security state
Branch address packets for change of processor state
Changes of state that are not indicated explicitly
ETM Architecture revision differences
Context ID packets
VMID packets, ETMv3.5
Exceptions when leaving Debug state
Processor reset
Other exceptions
Data tracing
Data packet types
Normal data packet
The A bit
BE bit
Size bits
Out-of-order packets
Out-of-order placeholder
The A bit
Tag bits
BE bit
Out-of-order data
Rules for generation of Out-of-order packets
64-bit values
Tracing LSMs
Value not traced packet
Data suppressed packet
Store failed packet
Jazelle data tracing
Data aborts
Asynchronous data aborts
Data-only mode, ETMv3.1 and later
Tracing LSM instructions in data-only mode
Possible wrong interpretation of CPRT trace in data-only mode
Data tracing options, ETMv3.3 and later
Detecting which data tracing options are available
Exceptions on Data Instructions
Additional trace features for ARMv7‑M processors, from ETMv3.4
Support for a large number of exceptions
Instructions that can be paused for continuation
Tracing continuation of an instruction during instruction-only trace
Automatic stack push on exception entry and pop on exception exit
Tracing return from an exception
Data tracing of return from exception
Tracing of exception return, ETMv3.5
Cancelling an exception return
Timestamping, ETMv3.5
Rules for generating timestamps
Cycle accuracy
Encoding of the timestamp value
Timestamp packet
Virtualization Extensions, ETMv3.5
Behavior of EmbeddedICE inputs, from ETMv3.4
EmbeddedICE watchpoint comparator input behavior
Default behavior of EmbeddedICE watchpoint inputs
Implementation of pulse and latch behavior of EmbeddedICE inputs
EmbeddedICE input usage examples
Synchronization
Frequency of synchronization
NonPeriodic synchronization
Periodic synchronization
A-sync, alignment synchronization
I-sync instruction synchronization
Use of I-sync packets in cycle-accurate mode
Normal I-sync packet
The Alternative instruction set bit, ETMv3.3 and later
Normal I-sync with cycle count packet
Load/Store in Progress (LSiP) I-sync packet
Load/Store in Progress (LSiP) I-sync with cycle count packet
Data-only I-sync packet
Reason codes
D-sync, data address synchronization
Trace port interface
Trigger
Ignore
FIFO draining
Tracing through regions with no code image
Cycle-accurate tracing
Tracing long gaps in cycle-accurate trace
Support for cycle-accurate tracing, ETMv3.3 and later
ETMv2 and ETMv3 compared
ETMv2 PIPESTAT encodings and ETMv3 P-headers compared
ETMv2 TFO packets and ETMv3 I-sync packets compared
Trace Port Physical Interface
Target system connector
Target connector pinouts
Assignment of trace information pins between ETM architecture versions
Single target connector pinout
Pipeline status seen by old TPAs, ETMv3.0 upwards
Wider trace ports, ETMv3.0 upwards
Dual target connector pinout
Asynchronous trace ports
Synchronous trace ports
Multiplexed trace port, single target connector pinout (ETMv1.x and ETMv2.x)
Demultiplexed trace port target connector pinout
Signal descriptions
EXTTRIG input
VTRef output
VSupply output
nTRST input
TDI input
TMS input
TCK input
RTCK output
TDO output
nSRST input
DBGRQ input
DBGACK output
VDD input
Connector placement
Connector orientation
Dual connector placement
Timing specifications
Half-rate clocking mode
Signal level specifications
Other target requirements
JTAG control connector
Tracing Dynamically Loaded Images
About tracing dynamically-loaded code
Simple overlay support
Software support for Context ID
Hardware support for Context ID
ETM Quick Reference Information
ETM event resources
Resource identification and event encoding
Resource control registers
Summary of implementation defined ETM features
Architecture Version Information
ETMv1
ETMv1.0 to ETMv1.1
Programmers’ model
ETMv1.1 to ETMv1.2
Controlling tracing
Programmers’ model
Signal protocol
ETMv1.2 to ETMv1.3
Programmers’ model
Signal protocol
ETMv2
ETMv1.3 to ETMv2.0
Controlling tracing
Programmers’ model
Signal protocol
ETMv2.0 to ETMv2.1
Programmers’ model
Signal protocol
ETMv3
ETMv2.1 to ETMv3.0
Programmers’ model
Signal protocol
ETMv3.0 to ETMv3.1
Programmers’ model
Signal protocol
ETMv3.1 to ETMv3.2
Programmers’ model
Signal protocol
ETMv3.2 to ETMv3.3
Programmers’ model
Signal protocol
Clarification of descriptions of features from earlier ETM versions
ETMv3.3 to ETMv3.4
Programmers’ model
Signal protocol
Clarification of descriptions of features from earlier ETM versions
ETMv3.4 to ETMv3.5
Programmers’ model
Signal protocol
Clarification of descriptions of features from earlier ETM versions
Glossary
Arm® Debug Interface Architecture Specification ADIv5.0 to ADIv5.2 Architecture Specification
Documentation placeholder
High Speed Serial Trace Port Architecture Specification
Documentation placeholder
ARM Generic Interrupt Controller Architecture Specification
Version 3.0/4.0
Arm® Generic Interrupt Controller Architecture Specification Reference Manual
Documentation placeholder
Version 2.0
ARM Generic Interrupt Controller Architecture Specification
Documentation placeholder
System Memory Management Unit Architecture Specification
Version 3.0, 3.1 and 3.2
SMMU Architecture Specification
Arm® System Memory Management Unit Architecture Specification SMMU architecture versions 3.0, 3.1 and 3.2
Documentation placeholder
Version 2.0
SMMU Architecture Specification (Issue D.c)
PDF version
Version 1.0
SMMU Architecture Specification
Documentation placeholder
SMMU 64KB Translation Granule Supplement
Documentation placeholder
ARM Software development tools
Application Binary Interface (ABI) for the ARM Architecture
ABI for the ARM 32-bit Architecture
ABI Introduction
PDF version
ABI Advisory Note 1
PDF version
Procedure Call Standard for the ARM Architecture Documentation
PDF version
ELF for the ARM Architecture Documentation
PDF version
DWARF for the ARM Architecture
PDF version
Base Platform ABI for the ARM Architecture
PDF version
C++ ABI for the ARM architecture Documentation
PDF version
Exception handling ABI for the ARM architecture Documentation
PDF version
Run-time ABI for the ARM Architecture
PDF version
C Library ABI for the ARM architecture Documentation
PDF version
Support for Debugging Overlaid Programs
PDF version
Addenda to, and Errata in, the ABI for the ARM Architecture Documentation
PDF version
Differences between v1 and v2 of the ABI for the ARM Architecture
PDF version
ABI for the ARM 64-bit Architecture
Release 1.1
Procedure Call Standard for the ARM 64-bit Architecture (AArch64) ARM IHI 0055C_beta, current through AArch64 ABI release 1.0
PDF version
ELF for the ARM® 64-bit Architecture (AArch64) ARM IHI 0056C_beta, current through AArch64 ABI release 1.0
PDF version
Release 1.0
Procedure Call Standard for the ARM 64-bit Architecture (AArch64) AArch64 ABI release 1.0
PDF version
ELF for the ARM 64-bit Architecture (AArch64) AArch64 ABI release 1.0
PDF version
DWARF for the ARM 64-bit Architecture (AArch64) AArch64 ABI release 1.0
PDF version
C++ Application Binary Interface Standard for the ARM 64-bit Architecture AArch64 ABI release 1.0
PDF version
ABI for the ARM 64-bit Architecture with SVE Support
Release 0.0
Procedure Call Standard for the ARM 64-bit Architecture (AArch64) SVE support Specification
PDF version
DWARF for the ARM® 64-bit Architecture (AArch64) with SVE support Specification
PDF version
ARM Compiler 4 and 5
Version 5.06
ARM Compiler 5.06u2 Release Notes
Introduction
Installation Instructions
Uninstall
Documentation
Feedback and Support
Release History and Changes
ARM Compiler 5.06u1 Release Notes
Introduction
Installation Instructions
Uninstall
Documentation
Feedback and Support
Release History and Changes
ARM Compiler 5.06 Release Notes
Introduction
Installation Instructions
Uninstall
Documentation
Feedback and Support
Release History and Changes
ARM Compiler Getting Started Guide
Preface
About this book
Using this book
Glossary
Typographic conventions
Feedback
Feedback on this product
Feedback on content
Other information
Overview of ARM Compiler
About ARM Compiler
Summary of ARM Compiler tools
Host platform support for ARM Compiler
Standards compliance in ARM Compiler
Compliance with the ABI for the ARM Architecture (Base Standard)
Supporting software
Important limitations of ARM Compiler
ARM architectures supported by the toolchain
ARM Compiler support on 64-bit host platforms
Considerations when using the 64-bit linker
Changing to the 64-bit linker (standalone product)
About the toolchain documentation
Licensed features of ARM Compiler
GCC compatibility provided by ARM Compiler
Toolchain environment variables
Environment variables used by the toolchain
TMP and TMPDIR environment variables for temporary file directories
Portability of source files between hosts
About specifying Cygwin paths in compilation tools on Windows
Rogue Wave documentation
Further reading
Getting Started with the Compilation Tools
About the ARM compilation tools
About specifying command-line options
Methods of specifying command-line options
Special characters on the command line
Rules for specifying command-line options
Order of options on the command line
Precedence of command-line options when using them in a text file
Autocompletion of command-line options
The ARM compiler command
The ARM linker command
The ARM assembler command
The fromelf image converter command
Getting Started Guide Document Revisions
Revisions for Getting Started Guide
ARM Compiler Errors and Warnings Reference Guide
Preface
About this book
Using this book
Glossary
Typographic conventions
Feedback
Feedback on this product
Feedback on content
Other information
C and C++ Compiler Errors and Warnings
Suppressing armcc error and warning messages
List of the armcc error and warning messages
Licensing Errors and Warnings
List of the licensing error and warning messages
Assembler Errors and Warnings
List of the armasm error and warning messages
Linker Errors and Warnings
Suppressing armlink error and warning messages
List of the armlink error and warning messages
ELF Image Converter Errors and Warnings
List of the fromelf error and warning messages
Librarian Errors and Warnings
List of the armar error and warning messages
Other Errors and Warnings
Internal faults and other unexpected failures
List of other error and warning messages
Errors and Warnings Reference Guide Document Revisions
Revisions for Errors and Warnings Reference Guide
ARM Compiler fromelf User Guide
Preface
About this book
Using this book
Glossary
Typographic conventions
Feedback
Feedback on this product
Feedback on content
Other information
Overview of the fromelf Image Converter
About the fromelf image converter
fromelf execution modes
Getting help on the fromelf command
fromelf command-line syntax
Using fromelf
General considerations when using fromelf
Examples of processing ELF files in an archive
Options to protect code in image files with fromelf
Options to protect code in object files with fromelf
Option to print specific details of ELF files
Using fromelf to find where a symbol is placed in an executable ELF image
fromelf Command-line Options
--base [[object_file::]load_region_ID=]num
--bin
--bincombined
--bincombined_base=address
--bincombined_padding=size,num
--cad
--cadcombined
--compare=option[,option,…]
--continue_on_error
--cpu=list
--cpu=name
--datasymbols
--debugonly
--decode_build_attributes
--diag_error=tag[,tag,…]
--diag_remark=tag[,tag,…]
--diag_style={arm|ide|gnu}
--diag_suppress=tag[,tag,…]
--diag_warning=tag[,tag,…]
--disassemble
--dump_build_attributes
--elf
--emit=option[,option,…]
--expandarrays
--extract_build_attributes
--fieldoffsets
--fpu=list
--fpu=name
--globalize=option[,option,…]
--help
--hide=option[,option,…]
--hide_and_localize=option[,option,…]
--i32
--i32combined
--ignore_section=option[,option,…]
--ignore_symbol=option[,option,…]
--in_place
--info=topic[,topic,…]
input_file
--interleave=option
--linkview, --no_linkview
--localize=option[,option,…]
--m32
--m32combined
--only=section_name
--output=destination
--privacy
--qualify
--relax_section=option[,option,…]
--relax_symbol=option[,option,…]
--rename=option[,option,…]
--select=select_options
--show=option[,option,…]
--show_and_globalize=option[,option,…]
--show_cmdline
--source_directory=path
--strip=option[,option,…]
--symbolversions, --no_symbolversions
--text
--version_number
--vhx
--via=file
--vsn
-w
--widthxbanks
Via File Syntax
Overview of via files
Via file syntax rules
fromelf Document Revisions
Revisions for fromelf Image Converter User Guide
ARM Compiler armlink User Guide
Preface
About this book
Using this book
Glossary
Typographic conventions
Feedback
Feedback on this product
Feedback on content
Other information
Overview of the Linker
About the linker
Summary of the linker features
What the linker can accept as input
What the linker outputs
Linker support for 64-bit host platforms
Linker command-line syntax
What the linker does when constructing an executable image
Linking Models Supported by armlink
Overview of linking models
Bare-metal linking model
Partial linking model
Base Platform Application Binary Interface (BPABI) linking model
Base Platform linking model
SysV linking model
Concepts common to both BPABI and SysV linking models
Image Structure and Generation
The structure of an ARM ELF image
Views of the image at each link stage
Input sections, output sections, regions, and program segments
Load view and execution view of an image
Methods of specifying an image memory map with the linker
Image entry points
The initial entry point for an image
Simple images
Types of simple image
Type 1 image structure, one load region and contiguous execution regions
Type 2 image structure, one load region and non-contiguous execution regions
Type 3 image structure, multiple load regions and non-contiguous execution regions
Section placement with the linker
Default section placement
Handling unassigned sections
Section placement with the FIRST and LAST attributes
Section alignment with the linker
Linker support for creating demand-paged files
Linker reordering of execution regions containing Thumb code
Linker-generated veneers
What is a veneer?
Veneer sharing
Veneer types
Generation of position independent to absolute veneers
Reuse of veneers when scatter-loading
Command-line options used to control the generation of C++ exception tables
Weak references and definitions
How the linker performs library searching, selection, and scanning
How the linker searches for the ARM standard libraries
Specifying user libraries when linking
How the linker resolves references
The strict family of linker options
Avoiding the BLX (immediate) instruction issue on an ARM1176JZ-S or ARM1176JZF-S processor
Linker Optimization Features
Elimination of common debug sections
Elimination of common groups or sections
Elimination of unused sections
Elimination of unused virtual functions
About linker feedback
Example of using linker feedback
Optimization with RW data compression
How the linker chooses a compressor
Options available to override the compression algorithm used by the linker
How compression is applied
Considerations when working with RW data compression
Function inlining with the linker
Factors that influence function inlining
About branches that optimize to a NOP
Linker reordering of tail calling sections
Restrictions on reordering of tail calling sections
Linker merging of comment sections
Getting Image Details
Options for getting information about linker-generated files
Identifying the source of some link errors
Example of using the --info linker option
How to find where a symbol is placed when linking
How to find the location of a symbol within the map file
Accessing and Managing Symbols with armlink
About mapping symbols
Linker-defined symbols
Region-related symbols
Types of region-related symbols
Image$$ execution region symbols
Load$$ execution region symbols
Load$$LR$$ load region symbols
Region name values when not scatter-loading
Linker defined symbols and scatter files
Methods of importing linker-defined symbols in C and C++
Methods of importing linker-defined symbols in ARM assembly language
Section-related symbols
Types of section-related symbols
Image symbols
Input section symbols
Access symbols in another image
Creating a symdefs file
Outputting a subset of the global symbols
Reading a symdefs file
Symdefs file format
Edit the symbol tables with a steering file
Specifying steering files on the linker command-line
Steering file command summary
Steering file format
Hide and rename global symbols with a steering file
Use of $Super$$ and $Sub$$ to patch symbol definitions
Scatter-loading Features
The scatter-loading mechanism
Overview of scatter-loading
When to use scatter-loading
Linker-defined symbols that are not defined when scatter-loading
Specifying stack and heap using the scatter file
Scatter-loading command-line options
Scatter-loading images with a simple memory map
Scatter-loading images with a complex memory map
Root execution regions
Root execution region and the initial entry point
Root execution regions and the ABSOLUTE attribute
Root execution regions and the FIXED attribute
Methods of placing functions and data at specific addresses
Placing functions and data at specific addresses
Example of how to place a variable at a specific address without scatter-loading
Example of how to place a variable in a named section with scatter-loading
Example of how to place a variable at a specific address with scatter-loading
Placement of code and data with __attribute__((section("name")))
Placement of __at sections at a specific address
Restrictions on placing __at sections
Automatic placement of __at sections
Manual placement of __at sections
Placement of a key in flash memory with an __at section
Mapping a structure over a peripheral register with an __at section
Example of how to explicitly place a named section with scatter-loading
Placement of unassigned sections with the .ANY module selector
Placement rules when using multiple .ANY selectors
Command-line options for controlling the placement of input sections for multiple .ANY selectors
Prioritization of .ANY sections
Specify the maximum region size permitted for placing unassigned sections
Examples of using placement algorithms for .ANY sections
Example of next_fit algorithm showing behavior of full regions, selectors, and priority
Examples of using sorting algorithms for .ANY sections
Behavior when .ANY sections overflow because of linker-generated content
Placement of veneer input sections in a scatter file
Placement of sections with overlays
Reserving an empty region
Placement of ARM C and C++ library code
Specifying ARM standard C and C++ libraries in a scatter file
Example of placing code in a root region
Example of placing ARM C library code
Example of placing ARM C++ library code
Example of placing ARM library helper functions
Creation of regions on page boundaries
Overalignment of execution regions and input sections
Preprocessing of a scatter file
Example of using expression evaluation in a scatter file to avoid padding
Equivalent scatter-loading descriptions for simple images
Command-line options for creating simple images
Type 1 image, one load region and contiguous execution regions
Type 2 image, one load region and non-contiguous execution regions
Type 3 image, multiple load regions and non-contiguous execution regions
How the linker resolves multiple matches when processing scatter files
How the linker resolves path names when processing scatter files
Scatter file to ELF mapping
Scatter File Syntax
BNF notation used in scatter-loading description syntax
Syntax of a scatter file
Load region descriptions
Components of a load region description
Syntax of a load region description
Load region attributes
Inheritance rules for load region address attributes
Inheritance rules for the RELOC address attribute
Considerations when using a relative address +offset for a load region
Execution region descriptions
Components of an execution region description
Syntax of an execution region description
Execution region attributes
Inheritance rules for execution region address attributes
Considerations when using a relative address +offset for execution regions
Input section descriptions
Components of an input section description
Syntax of an input section description
Examples of module and input section specifications
Expression evaluation in scatter files
Expression usage in scatter files
Expression rules in scatter files
Execution address built-in functions for use in scatter files
ScatterAssert function and load address related functions
Symbol related function in a scatter file
AlignExpr(expr, align) function
GetPageSize() function
SizeOfHeaders() function
Example of aligning a base address in execution space but still tightly packed in load space
Scatter files containing relative base address load regions and a ZI execution region
GNU ld Script Support in armlink
About GNU ld script support
Summary of GNU ld script support and restrictions
Considerations when linking images and shared objects with ld scripts
Using ld scripts when linking partial objects
Typical use cases for using ld scripts with armlink
Important ld script commands that are implemented in armlink
Specific restrictions for using ld scripts with armlink
Recommendations for using ld scripts with armlink
Default GNU ld scripts used by armlink
Default ld script when building an executable
Default ld script when building a shared object
Default ld script when building a partially linked object
Example GNU ld script for linking an ARM Linux executable
Example GNU ld script for linking an ARM Linux shared object
Example GNU ld script for linking partial objects
BPABI and SysV Shared Libraries and Executables
About the Base Platform Application Binary Interface (BPABI)
Platforms supported by the BPABI
Features common to all BPABI models
About importing and exporting symbols for BPABI models
Symbol visibility for BPABI models
Automatic import and export for BPABI models
Manual import and export for BPABI models
Symbol versioning for BPABI models
RW compression for BPABI models
SysV memory model
Customization of the SysV standard memory model
Automatic dynamic symbol table rules in the SysV memory model
Symbol definitions defined for SysV compatibility with glibc
Addressing modes in the SysV memory model
Thread local storage in the SysV memory model
Linker options for SysV models
Linker command-line options for the SysV memory model
Changes to command-line defaults with the SysV memory model
Bare metal and DLL-like memory models
BPABI standard memory model
Customization of the BPABI standard memory model
Linker command-line options for bare metal and DLL-like models
Mandatory symbol versioning in the BPABI DLL-like model
Automatic dynamic symbol table rules in the BPABI DLL-like model
Addressing modes in the BPABI DLL-like model
C++ initialization in the BPABI DLL-like model
Symbol versioning
Overview of symbol versioning
Embedded symbols
The symbol versioning script file
Example of creating versioned symbols
Linker options for enabling implicit symbol versioning
Features of the Base Platform Linking Model
Restrictions on the use of scatter files with the Base Platform model
Scatter files for the Base Platform linking model
Placement of PLT sequences with the Base Platform model
Linker Command-line Options
--add_needed, --no_add_needed
--add_shared_references, --no_add_shared_references
--any_contingency
--any_placement=algorithm
--any_sort_order=order
--api, --no_api
--arm_linux
--arm_only
--as_needed, --no_as_needed
--autoat, --no_autoat
--base_platform
--be8
--be32
--bestdebug, --no_bestdebug
--blx_arm_thumb, --no_blx_arm_thumb
--blx_thumb_arm, --no_blx_thumb_arm
--bpabi
--branchnop, --no_branchnop
--callgraph, --no_callgraph
--callgraph_file=filename
--callgraph_output=fmt
--callgraph_subset=symbol[,symbol,...]
--cgfile=type
--cgsymbol=type
--cgundefined=type
--combreloc, --no_combreloc
--comment_section, --no_comment_section
--compress_debug, --no_compress_debug
--cpp_compat linker option
--cppinit, --no_cppinit
--cpu=list
--cpu=name
--crosser_veneershare, --no_crosser_veneershare
--datacompressor=opt
--debug, --no_debug
--diag_error=tag[,tag,…]
--diag_remark=tag[,tag,…]
--diag_style=arm|ide|gnu
--diag_suppress=tag[,tag,…]
--diag_warning=tag[,tag,…]
--dll
--dynamic_debug
--dynamic_linker=name
--eager_load_debug, --no_eager_load_debug
--edit=file_list
--emit_debug_overlay_relocs
--emit_debug_overlay_section
--emit_non_debug_relocs
--emit_relocs
--entry=location
--errors=filename
--exceptions, --no_exceptions
--exceptions_tables=action
--execstack, --no_execstack
--export_all, --no_export_all
--export_dynamic, --no_export_dynamic
--feedback=filename
--feedback_image=option
--feedback_type=type
--filtercomment, --no_filtercomment
--fini=symbol
--first=section_id
--force_explicit_attr
--force_so_throw, --no_force_so_throw
--fpic
--fpu=list
--fpu=name
--gnu_linker_defined_syms
--help
--import_unresolved, --no_import_unresolved
--info=topic[,topic,…]
--info_lib_prefix=opt
--init=symbol
--inline, --no_inline
--inline_type=type
--inlineveneer, --no_inlineveneer
input-file-list
--keep=section_id
--largeregions, --no_largeregions
--last=section_id
--ldpartial
--legacyalign, --no_legacyalign
--libpath=pathlist
--library=name
--library_type=lib
--linker_script=ld_script
--linux_abitag=version_id
--list=filename
--list_mapping_symbols, --no_list_mapping_symbols
--load_addr_map_info, --no_load_addr_map_info
--locals, --no_locals
--mangled, --unmangled
--map, --no_map
--match=crossmangled
--max_er_extension=size
--max_veneer_passes=value
--max_visibility=type
--merge, --no_merge
--muldefweak, --no_muldefweak
-o filename, --output=filename
--output_float_abi=option
--override_visibility
--pad=num
--paged
--pagesize=pagesize
--partial
--piveneer, --no_piveneer
--pltgot=type
--pltgot_opts=mode
--predefine="string"
--prelink_support, --no_prelink_support
--privacy
--reduce_paths, --no_reduce_paths
--ref_cpp_init, --no_ref_cpp_init
--reloc
--remarks
--remove, --no_remove
--ro_base=address
--ropi
--rosplit
--runpath=pathlist
--rw_base=address
--rwpi
--scanlib, --no_scanlib
--scatter=filename
--search_dynamic_libraries, --no_search_dynamic_libraries
--section_index_display=type
--shared
--show_cmdline
--show_full_path
--show_parent_lib
--show_sec_idx
--soname=name
--sort=algorithm
--split
--startup=symbol, --no_startup
--strict
--strict_enum_size, --no_strict_enum_size
--strict_flags, --no_strict_flags
--strict_ph, --no_strict_ph
--strict_relocations, --no_strict_relocations
--strict_symbols, --no_strict_symbols
--strict_visibility, --no_strict_visibility
--strict_wchar_size, --no_strict_wchar_size
--symbolic
--symbols, --no_symbols
--symdefs=filename
--symver_script=filename
--symver_soname
--sysroot=path
--sysv
--tailreorder, --no_tailreorder
--thumb2_library, --no_thumb2_library
--tiebreaker=option
--unaligned_access, --no_unaligned_access
--undefined=symbol
--undefined_and_export=symbol
--unresolved=symbol
--use_definition_visibility
--use_sysv_default_script, --no_use_sysv_default_script
--userlibpath=pathlist
--veneerinject, --no_veneerinject
--veneer_inject_type=type
--veneer_pool_size=size
--veneershare, --no_veneershare
--verbose
--version_number
--vfemode=mode
--via=filename
--vsn
--xo_base=address
--xref, --no_xref
--xrefdbg, --no_xrefdbg
--xref{from|to}=object(section)
--zi_base=address
Linker Steering File Command Reference
EXPORT steering file command
HIDE steering file command
IMPORT steering file command
RENAME steering file command
REQUIRE steering file command
RESOLVE steering file command
SHOW steering file command
Via File Syntax
Overview of via files
Via file syntax rules
armlink Document Revisions
Revisions for armlink User Guide
ARM Compiler Migration and Compatibility Guide
Preface
About this book
Using this book
Glossary
Typographic conventions
Feedback
Feedback on this product
Feedback on content
Other information
Overview of Compatibility
Compatibility between ARM Compiler versions
Configuration Information for Different Versions of the ARM Compilation Tools
FlexNet versions supported
GCC versions emulated
Cygwin versions supported
Migrating from ARM Compiler v5.05 to v5.06
Compatibility of ARM Compiler v5.06 with legacy objects and libraries
Compiler changes between ARM Compiler v5.05 and v5.06
#pragma arm section and inline functions
GCC default version changed
__ldrex and __strex intrinsics deprecated
Migrating from ARM Compiler v5.04 to v5.05
Compatibility of ARM Compiler v5.05 with legacy objects and libraries
Compatibility of code compiled with C++11 with code compiled with C++03
Use of C++11 with the ARM C++ Standard Libraries
Compiler changes between ARM Compiler v5.04 and v5.05
C++ name mangling differences in ARM Compiler v5.05
Non-type non-dependent template arguments
Substitution of _Complex types
Const-volatile-qualified non-member function type as template argument
lvalue of function type used as non-type template argument
Migrating from ARM Compiler v5.03 to v5.04
Compatibility of ARM Compiler v5.04 with legacy objects and libraries
Documentation changes between ARM Compiler v5.03 and v5.04
Migrating from ARM Compiler v5.02 to v5.03
Compatibility of ARM Compiler v5.03 with legacy objects and libraries
Compiler changes between ARM Compiler v5.02 and v5.03
Documentation changes between ARM Compiler v5.02 and v5.03
Migrating from ARM Compiler v5.0 to v5.01 or later
Compatibility of ARM Compiler v5.01 with legacy objects and libraries
General changes between ARM Compiler v5.0 and v5.01 or later
Documentation changes between ARM Compiler v5.0 and v5.01 or later
Migrating from ARM Compiler v4.1 Patch 3 or later to v5.0
Compatibility of ARM Compiler v5.0 with legacy objects and libraries
General changes between ARM Compiler v4.1 Patch 3 or later and v5.0
Compiler changes between ARM Compiler v4.1 Patch 3 or later and v5.0
Linker changes between ARM Compiler v4.1 Patch 3 or later and v5.0
Documentation changes between ARM Compiler v4.1 Patch 3 or later and v5.0
Migrating from ARM Compiler v4.1 build 561 to v4.1 Patch 3 or later
Compatibility of ARM Compiler v4.1 Patch 3 with legacy objects and libraries
C and C++ library changes between ARM Compiler v4.1 build 561 and v4.1 Patch 3 or later
Migrating from ARM Compiler v4.1 to v4.1 build 561
Compatibility of ARM Compiler v4.1 build 561 with legacy objects and libraries
Compiler changes between ARM Compiler v4.1 and v4.1 build 561
Linker changes between ARM Compiler v4.1 and v4.1 build 561
Assembler changes between ARM Compiler v4.1 and v4.1 build 561
C and C++ library changes between ARM Compiler v4.1 and v4.1 build 561
fromelf changes between ARM Compiler v4.1 and v4.1 build 561
Documentation changes between ARM Compiler v4.1 and v4.1 build 561
Migrating from RVCT v4.0 to ARM Compiler v4.1
General changes between RVCT v4.0 and ARM Compiler v4.1
Compiler changes between RVCT v4.0 and ARM Compiler v4.1
Linker changes between RVCT v4.0 and ARM Compiler v4.1
Assembler changes between RVCT v4.0 and ARM Compiler v4.1
C and C++ library changes between RVCT v4.0 and ARM Compiler v4.1
Migrating from RVCT v3.1 to RVCT v4.0
Default --gnu_version changed from 303000 (GCC 3.3) to 402000 (GCC 4.2)
General changes between RVCT v3.1 and RVCT v4.0
Changes to symbol visibility between RVCT v3.1 and RVCT v4.0
Compiler changes between RVCT v3.1 and RVCT v4.0
Linker changes between RVCT v3.1 and RVCT v4.0
Assembler changes between RVCT v3.1 and RVCT v4.0
fromelf changes between RVCT v3.1 and RVCT v4.0
C and C++ library changes between RVCT v3.1 and RVCT v4.0
Migrating from RVCT v3.0 to RVCT v3.1
General changes between RVCT v3.0 and RVCT v3.1
Assembler changes between RVCT v3.0 and RVCT v3.1
Linker changes between RVCT v3.0 and RVCT v3.1
Migrating from RVCT v2.2 to RVCT v3.0
General changes between RVCT v2.2 and RVCT v3.0
Compiler changes between RVCT v2.2 and RVCT v3.0
Linker changes between RVCT v2.2 and RVCT v3.0
C and C++ library changes between RVCT v2.2 and RVCT v3.0
Migration and Compatibility document revisions
Revisions for Migration and Compatibility Guide
ARM Compiler armasm User Guide
Preface
About this book
Using this book
Glossary
Typographic conventions
Feedback
Feedback on this product
Feedback on content
Other information
Overview of the Assembler
About the ARM Compiler toolchain assemblers
Key features of the assembler
How the assembler works
Directives that can be omitted in pass 2 of the assembler
Overview of the ARM Architecture
About the ARM architecture
ARM, Thumb, and ThumbEE instruction sets
Changing between ARM, Thumb, and ThumbEE state
Processor modes, and privileged and unprivileged software execution
Processor modes in ARMv6-M and ARMv7-M
NEON technology
VFP hardware
ARM registers
General-purpose registers
Register accesses
Predeclared core register names
Predeclared extension register names
Predeclared XScale register names
Predeclared coprocessor names
Program Counter
Application Program Status Register
The Q flag
Current Program Status Register
Saved Program Status Registers
ARM and Thumb instruction set overview
Access to the inline barrel shifter
Structure of Assembly Language Modules
Syntax of source lines in assembly language
Literals
ELF sections and the AREA directive
An example ARM assembly language module
Writing ARM Assembly Language
About the Unified Assembler Language
Register usage in subroutine calls
Load immediate values
Load immediate values using MOV and MVN
Load immediate values using MOV32
Load immediate values using LDR Rd, =const
Literal pools
Load addresses into registers
Load addresses to a register using ADR
Load addresses to a register using ADRL
Load addresses to a register using LDR Rd, =label
Other ways to load and store registers
Load and store multiple register instructions
Load and store multiple register instructions in ARM and Thumb
Stack implementation using LDM and STM
Stack operations for nested subroutines
Block copy with LDM and STM
Memory accesses
The Read-Modify-Write operation
Optional hash with immediate constants
Use of macros
Test-and-branch macro example
Unsigned integer division macro example
Instruction and directive relocations
Symbol versions
Frame directives
Exception tables and Unwind tables
Assembly language changes after RVCT v2.1
Condition Codes
Conditional instructions
Conditional execution in ARM state
Conditional execution in Thumb state
Updates to the condition flags
Condition code suffixes and related flags
Comparison of condition code meanings in integer and floating-point code
Benefits of using conditional execution
Example showing the benefits of using conditional instructions
Optimization for execution speed
Using the Assembler
armasm command-line syntax
Specify command-line options with an environment variable
Using stdin to input source code to the assembler
Built-in variables and constants
Identifying versions of armasm in source code
Diagnostic messages
Interlocks diagnostics
Automatic IT block generation
Thumb branch target alignment
Thumb code size diagnostics
ARM and Thumb instruction portability diagnostics
Instruction width diagnostics
Two pass assembler diagnostics
Conditional assembly
Using the C preprocessor
Address alignment
Instruction width selection in Thumb
Symbols, Literals, Expressions, and Operators
Symbol naming rules
Variables
Numeric constants
Assembly time substitution of variables
Register-relative and PC-relative expressions
Labels
Labels for PC-relative addresses
Labels for register-relative addresses
Labels for absolute addresses
Numeric local labels
Syntax of numeric local labels
String expressions
String literals
Numeric expressions
Syntax of numeric literals
Syntax of floating-point literals
Logical expressions
Logical literals
Unary operators
Binary operators
Multiplicative operators
String manipulation operators
Shift operators
Addition, subtraction, and logical operators
Relational operators
Boolean operators
Operator precedence
Difference between operator precedence in assembly language and C
NEON Programming
Architecture support for NEON
Half-precision extension for NEON
Fused Multiply-Add extension for NEON
Extension register bank mapping in NEON
NEON views of the extension register bank
Load values to NEON registers
Conditional execution of NEON instructions
Floating-point exceptions in NEON
NEON data types
Extended notation extension for NEON
NEON vectors
Normal, long, wide, and narrow NEON operation
Saturating NEON instructions
NEON scalars
Polynomial arithmetic over {0,1}
NEON system registers
Flush-to-zero mode in NEON
NEON operations not affected by flush-to-zero mode
When to use flush-to-zero mode in NEON
The effects of using flush-to-zero mode in NEON
VFP Programming
Architecture support for VFP
Half-precision extension for VFP
Fused Multiply-Add extension for VFP
Extension register bank mapping in VFP
VFP views of the extension register bank
Load values to VFP registers
Conditional execution of VFP instructions
Floating-point exceptions in VFP
VFP data types
Extended notation extension for VFP
VFP system registers
Flush-to-zero mode
When to use flush-to-zero mode in VFP
The effects of using flush-to-zero mode in VFP
VFP operations not affected by flush-to-zero mode
VFP vector mode
Vectors in the VFP extension register bank
VFP vector wrap-around
VFP vector stride
Restriction on vector length
Control of scalar, vector, and mixed operations
Overview of VFP directives and vector notation
Pre-UAL VFP syntax and mnemonics
Vector notation
VFPASSERT SCALAR
VFPASSERT VECTOR
Assembler Command-line Options
--16
--32
--apcs=qualifier…qualifier
--arm
--arm_only
--bi
--bigend
--brief_diagnostics, --no_brief_diagnostics
--checkreglist
--comment_section, --no_comment_section
--compatible=name
--cpreproc
--cpreproc_opts=option[,option,…]
--cpu=list
--cpu=name
--debug
--depend=dependfile
--depend_format=string
--diag_error=tag[,tag,…]
--diag_remark=tag[,tag,…]
--diag_style={arm|ide|gnu}
--diag_suppress=tag[,tag,…]
--diag_warning=tag[,tag,…]
--dllexport_all
--dwarf2
--dwarf3
--errors=errorfile
--execstack, --no_execstack
--execute_only
--exceptions, --no_exceptions
--exceptions_unwind, --no_exceptions_unwind
--fpmode=model
--fpu=list
--fpu=name
-g
--help
-idir[,dir, …]
--keep
--length=n
--li
--library_type=lib
--list=file
--list=
--littleend
-m
--maxcache=n
--md
--no_code_gen
--no_esc
--no_hide_all
--no_regs
--no_terse
--no_warn
-o filename
--pd
--predefine "directive"
--reduce_paths, --no_reduce_paths
--regnames
--report-if-not-wysiwyg
--show_cmdline
--split_ldm
--thumb
--thumbx
--unaligned_access, --no_unaligned_access
--unsafe
--untyped_local_labels
--version_number
--via=filename
--vsn
--width=n
--xref
ARM and Thumb Instructions
ARM and Thumb instruction summary
Instruction width specifiers
Flexible second operand (Operand2)
Syntax of Operand2 as a constant
Syntax of Operand2 as a register with optional shift
Shift operations
Saturating instructions
Condition code suffixes
ADC
ADD
ADR (PC-relative)
ADR (register-relative)
ADRL pseudo-instruction
AND
ASR
B
BFC
BFI
BIC
BKPT
BL
BLX
BX
BXJ
CBZ and CBNZ
CDP and CDP2
CLREX
CLZ
CMP and CMN
CPS
CPY pseudo-instruction
DBG
DMB
DSB
EOR
ERET
HVC
ISB
IT
LDC and LDC2
LDM
LDR (immediate offset)
LDR (PC-relative)
LDR (register offset)
LDR (register-relative)
LDR pseudo-instruction
LDR, unprivileged
LDREX
LSL
LSR
MAR
MCR and MCR2
MCRR and MCRR2
MIA, MIAPH, and MIAxy
MLA
MLS
MOV
MOV32 pseudo-instruction
MOVT
MRA
MRC and MRC2
MRRC and MRRC2
MRS (PSR to general-purpose register)
MRS (system coprocessor register to ARM register)
MSR (ARM register to system coprocessor register)
MSR (general-purpose register to PSR)
MUL
MVN
NEG pseudo-instruction
NOP
ORN (Thumb only)
ORR
PKHBT and PKHTB
PLD, PLDW, and PLI
POP
PUSH
QADD
QADD8
QADD16
QASX
QDADD
QDSUB
QSAX
QSUB
QSUB8
QSUB16
RBIT
REV
REV16
REVSH
RFE
ROR
RRX
RSB
RSC
SADD8
SADD16
SASX
SBC
SBFX
SDIV
SEL
SETEND
SEV
SHADD8
SHADD16
SHASX
SHSAX
SHSUB8
SHSUB16
SMC
SMLAxy
SMLAD
SMLAL
SMLALD
SMLALxy
SMLAWy
SMLSD
SMLSLD
SMMLA
SMMLS
SMMUL
SMUAD
SMULxy
SMULL
SMULWy
SMUSD
SRS
SSAT
SSAT16
SSAX
SSUB8
SSUB16
STC and STC2
STM
STR (immediate offset)
STR (register offset)
STR, unprivileged
STREX
SUB
SUBS pc, lr
SVC
SWP and SWPB
SXTAB
SXTAB16
SXTAH
SXTB
SXTB16
SXTH
SYS
TBB and TBH
TEQ
TST
UADD8
UADD16
UASX
UBFX
UDIV
UHADD8
UHADD16
UHASX
UHSAX
UHSUB8
UHSUB16
UMAAL
UMLAL
UMULL
UND pseudo-instruction
UQADD8
UQADD16
UQASX
UQSAX
UQSUB8
UQSUB16
USAD8
USADA8
USAT
USAT16
USAX
USUB8
USUB16
UXTAB
UXTAB16
UXTAH
UXTB
UXTB16
UXTH
WFE
WFI
YIELD
NEON Instructions
Summary of NEON instructions
Summary of shared NEON and VFP instructions
Interleaving provided by load and store element and structure instructions
Alignment restrictions in load and store element and structure instructions
VABA and VABAL
VABD and VABDL
VABS
VACLE, VACLT, VACGE and VACGT
VADD
VADDHN
VADDL and VADDW
VAND (immediate)
VAND (register)
VBIC (immediate)
VBIC (register)
VBIF
VBIT
VBSL
VCEQ (immediate #0)
VCEQ (register)
VCGE (immediate #0)
VCGE (register)
VCGT (immediate #0)
VCGT (register)
VCLE (immediate #0)
VCLE (register)
VCLS
VCLT (immediate #0)
VCLT (register)
VCLZ
VCNT
VCVT (between fixed-point or integer, and floating-point)
VCVT (between half-precision and single-precision floating-point)
VDUP
VEOR
VEXT
VFMA, VFMS
VHADD
VHSUB
VLDn (single n-element structure to one lane)
VLDn (single n-element structure to all lanes)
VLDn (multiple n-element structures)
VLDM
VLDR
VLDR (post-increment and pre-decrement)
VLDR pseudo-instruction
VMAX and VMIN
VMLA
VMLA (by scalar)
VMLAL (by scalar)
VMLAL
VMLS (by scalar)
VMLS
VMLSL
VMLSL (by scalar)
VMOV (floating-point)
VMOV (immediate)
VMOV (register)
VMOV (between two ARM registers and a 64-bit extension register)
VMOV (between an ARM register and a NEON scalar)
VMOVL
VMOVN
VMOV2
VMRS
VMSR
VMUL
VMUL (by scalar)
VMULL
VMULL (by scalar)
VMVN (register)
VMVN (immediate)
VNEG
VORN (register)
VORN (immediate)
VORR (register)
VORR (immediate)
VPADAL
VPADD
VPADDL
VPMAX and VPMIN
VPOP
VPUSH
VQABS
VQADD
VQDMLAL and VQDMLSL (by vector or by scalar)
VQDMULH (by vector or by scalar)
VQDMULL (by vector or by scalar)
VQMOVN and VQMOVUN
VQNEG
VQRDMULH (by vector or by scalar)
VQRSHL (by signed variable)
VQRSHRN and VQRSHRUN (by immediate)
VQSHL (by signed variable)
VQSHL and VQSHLU (by immediate)
VQSHRN and VQSHRUN (by immediate)
VQSUB
VRADDHN
VRECPE
VRECPS
VREV16, VREV32, and VREV64
VRHADD
VRSHL (by signed variable)
VRSHR (by immediate)
VRSHRN (by immediate)
VRSQRTE
VRSQRTS
VRSRA (by immediate)
VRSUBHN
VSHL (by immediate)
VSHL (by signed variable)
VSHLL (by immediate)
VSHR (by immediate)
VSHRN (by immediate)
VSLI
VSRA (by immediate)
VSRI
VSTM
VSTn (multiple n-element structures)
VSTn (single n-element structure to one lane)
VSTR
VSTR (post-increment and pre-decrement)
VSUB
VSUBHN
VSUBL and VSUBW
VSWP
VTBL and VTBX
VTRN
VTST
VUZP
VZIP
VFP Instructions
Summary of VFP instructions
VABS (floating-point)
VADD (floating-point)
VCMP, VCMPE
VCVT (between single-precision and double-precision)
VCVT (between floating-point and integer)
VCVT (between floating-point and fixed-point)
VCVTB, VCVTT (half-precision extension)
VDIV
VFMA, VFMS, VFNMA, VFNMS (floating-point)
VLDM (floating-point)
VLDR (floating-point)
VLDR (post-increment and pre-decrement, floating-point)
VLDR pseudo-instruction
VMLA (floating-point)
VMLS (floating-point)
VMOV (floating-point)
VMOV (between one ARM register and single precision VFP)
VMOV (between two ARM registers and one or two extension registers)
VMOV (between an ARM register and half a double precision VFP register)
VMRS
VMSR
VMUL (floating-point)
VNEG (floating-point)
VNMLA (floating-point)
VNMLS (floating-point)
VNMUL (floating-point)
VPOP (floating-point)
VPUSH (floating-point)
VSQRT
VSTM (floating-point)
VSTR (floating-point)
VSTR (post-increment and pre-decrement, floating-point)
VSUB (floating-point)
Wireless MMX Technology Instructions
About Wireless MMX Technology instructions
WRN and WCN directives to support Wireless MMX Technology
Frame directives and Wireless MMX Technology
Wireless MMX load and store instructions
Wireless MMX Technology and XScale instructions
Wireless MMX instructions
Wireless MMX pseudo-instructions
Directives Reference
Alphabetical list of directives
About assembly control directives
About frame directives
ALIAS
ALIGN
AREA
ARM or CODE32
ASSERT
ATTR
CN
CODE16
COMMON
CP
DATA
DCB
DCD and DCDU
DCDO
DCFD and DCFDU
DCFS and DCFSU
DCI
DCQ and DCQU
DCW and DCWU
END
ENDFUNC or ENDP
ENTRY
EQU
EXPORT or GLOBAL
EXPORTAS
FIELD
FRAME ADDRESS
FRAME POP
FRAME PUSH
FRAME REGISTER
FRAME RESTORE
FRAME RETURN ADDRESS
FRAME SAVE
FRAME STATE REMEMBER
FRAME STATE RESTORE
FRAME UNWIND ON
FRAME UNWIND OFF
FUNCTION or PROC
GBLA, GBLL, and GBLS
GET or INCLUDE
IF, ELSE, ENDIF, and ELIF
IMPORT and EXTERN
INCBIN
INFO
KEEP
LCLA, LCLL, and LCLS
LTORG
MACRO and MEND
MAP
MEXIT
NOFP
OPT
QN, DN, and SN
RELOC
REQUIRE
REQUIRE8 and PRESERVE8
RLIST
RN
ROUT
SETA, SETL, and SETS
SPACE or FILL
THUMB
THUMBX
TTL and SUBT
WHILE and WEND
Via File Syntax
Overview of via files
Via file syntax rules
Assembler Document Revisions
Revisions for armasm User Guide
ARM Compiler ARM C and C++ Libraries and Floating-Point Support User Guide
Preface
About this book
Using this book
Glossary
Typographic conventions
Feedback
Feedback on this product
Feedback on content
Other information
The ARM C and C++ Libraries
Mandatory linkage with the C library
C and C++ runtime libraries
Summary of the C and C++ runtime libraries
Compliance with the Application Binary Interface (ABI) for the ARM architecture
Increasing portability of object files to other CLIBABI implementations
ARM C and C++ library directory structure
Selection of ARM C and C++ library variants based on build options
Thumb C libraries
C and C++ library features
C++ and C libraries and the std namespace
Multithreaded support in ARM C libraries
ARM C libraries and multithreading
ARM C libraries and reentrant functions
ARM C libraries and thread-safe functions
Use of static data in the C libraries
Use of the __user_libspace static data area by the C libraries
C library functions to access subsections of the __user_libspace static data area
Re-implementation of legacy function __user_libspace() in the C library
Management of locks in multithreaded applications
How to ensure re-implemented mutex functions are called
Using the ARM C library in a multithreaded environment
Thread safety in the ARM C library
Thread safety in the ARM C++ library
The floating-point status word in a multithreaded environment
Support for building an application with the C library
Using the C library with an application
Using the C and C++ libraries with an application in a semihosting environment
Using $Sub$$ to mix semihosted and nonsemihosted I/O functionality
Using the libraries in a nonsemihosting environment
C++ exceptions in a non-semihosting environment
Direct semihosting C library function dependencies
Indirect semihosting C library function dependencies
C library API definitions for targeting a different environment
Support for building an application without the C library
Building an application without the C library
Creating an application as bare machine C without the C library
Integer and floating-point compiler functions and building an application without the C library
Bare machine integer C
Bare machine C with floating-point processing
Customized C library startup code and access to C library functions
Using low-level functions when exploiting the C library
Using high-level functions when exploiting the C library
Using malloc() when exploiting the C library
Tailoring the C library to a new execution environment
Initialization of the execution environment and execution of the application
C++ initialization, construction and destruction
Exceptions system initialization
Emergency buffer memory for exceptions
Library functions called from main()
Program exit and the assert macro
Assembler macros that tailor locale functions in the C library
Link time selection of the locale subsystem in the C library
ISO8859-1 implementation
Shift-JIS and UTF-8 implementation
Runtime selection of the locale subsystem in the C library
Definition of locale data blocks in the C library
LC_CTYPE data block
LC_COLLATE data block
LC_MONETARY data block
LC_NUMERIC data block
LC_TIME data block
Modification of C library functions for error signaling, error handling, and program exit
Stack and heap memory allocation and the ARM C and C++ libraries
Library heap usage requirements of the ARM C and C++ libraries
Choosing a heap implementation for memory allocation functions
Stack pointer initialization and heap bounds
Legacy support for __user_initial_stackheap()
Avoiding the heap and heap-using library functions supplied by ARM
Tailoring input/output functions in the C and C++ libraries
Target dependencies on low-level functions in the C and C++ libraries
The C library printf family of functions
The C library scanf family of functions
Redefining low-level library functions to enable direct use of high-level library functions in the C library
The C library functions fread(), fgets() and gets()
Re-implementing __backspace() in the C library
Re-implementing __backspacewc() in the C library
Redefining target-dependent system I/O functions in the C library
Tailoring non-input/output C library functions
Real-time integer division in the ARM libraries
ISO C library implementation definition
How the ARM C library fulfills ISO C specification requirements
mathlib error handling
ISO-compliant implementation of signals supported by the signal() function in the C library and additional type arguments
ISO-compliant C library input/output characteristics
Standard C++ library implementation definition
C library functions and extensions
Compiler generated and library-resident helper functions
C and C++ library naming conventions
Using macro__ARM_WCHAR_NO_IO to disable FILE declaration and wide I/O function prototypes
Using library functions with execute-only memory
The ARM C Micro-library
About microlib
Differences between microlib and the default C library
Library heap usage requirements of microlib
ISO C features missing from microlib
Building an application with microlib
Configuring the stack and heap for use with microlib
Entering and exiting programs linked with microlib
Tailoring the microlib input/output functions
Floating-point Support
About floating-point support
The software floating-point library, fplib
Calling fplib routines
fplib arithmetic on numbers in a particular format
fplib conversions between floats, long longs, doubles, and ints
fplib comparisons between floats and doubles
fplib C99 functions
Controlling the ARM floating-point environment
Floating-point functions for compatibility with Microsoft products
C99-compatible functions for controlling the ARM floating-point environment
C99 rounding mode and floating-point exception macros
Exception flag handling
Functions for handling rounding modes
Functions for saving and restoring the whole floating-point environment
Functions for temporarily disabling exceptions
ARM floating-point compiler extensions to the C99 interface
Writing a custom exception trap handler
Example of a custom exception handler
Exception trap handling by signals
Using C99 signaling NaNs provided by mathlib (_WANT_SNAN)
mathlib double and single-precision floating-point functions
IEEE 754 arithmetic
Basic data types for IEEE 754 arithmetic
Single precision data type for IEEE 754 arithmetic
Double precision data type for IEEE 754 arithmetic
Sample single precision floating-point values for IEEE 754 arithmetic
Sample double precision floating-point values for IEEE 754 arithmetic
IEEE 754 arithmetic and rounding
Exceptions arising from IEEE 754 floating-point arithmetic
Exception types recognized by the ARM floating-point environment
Using the Vector Floating-Point (VFP) support libraries
The C and C++ Library Functions reference
__aeabi_errno_addr()
alloca()
clock()
_clock_init()
__default_signal_handler()
errno
_findlocale()
_fisatty()
_get_lconv()
getenv()
_getenv_init()
__heapstats()
__heapvalid()
lconv structure
localeconv()
_membitcpybl(), _membitcpybb(), _membitcpyhl(), _membitcpyhb(), _membitcpywl(), _membitcpywb(), _membitmovebl(), _membitmovebb(), _membitmovehl(), _membitmovehb(), _membitmovewl(), _membitmovewb()
posix_memalign()
#pragma import(_main_redirection)
__raise()
_rand_r()
remove()
rename()
__rt_entry
__rt_errno_addr()
__rt_exit()
__rt_fp_status_addr()
__rt_heap_extend()
__rt_lib_init()
__rt_lib_shutdown()
__rt_raise()
__rt_stackheap_init()
setlocale()
_srand_r()
strcasecmp()
strncasecmp()
strlcat()
strlcpy()
_sys_close()
_sys_command_string()
_sys_ensure()
_sys_exit()
_sys_flen()
_sys_istty()
_sys_open()
_sys_read()
_sys_seek()
_sys_tmpnam()
_sys_write()
system()
time()
_ttywrch()
__user_heap_extend()
__user_heap_extent()
__user_setup_stackheap()
__vectab_stack_and_reset
wcscasecmp()
wcsncasecmp()
wcstombs()
Thread-safe C library functions
C library functions that are not thread-safe
Legacy function __user_initial_stackheap()
Floating-point Support Functions Reference
_clearfp()
_controlfp()
__fp_status()
gamma(), gamma_r()
__ieee_status()
j0(), j1(), jn(), Bessel functions of the first kind
significand(), fractional part of a number
_statusfp()
y0(), y1(), yn(), Bessel functions of the second kind
Libraries Document Revisions
Revisions for ARM C and C++ Libraries and Floating-Point Support User Guide
ARM Compiler Software Development Guide
Preface
About this book
Using this book
Glossary
Typographic conventions
Feedback
Feedback on this product
Feedback on content
Other information
Key Features of ARM Architecture Versions
About the ARM architectures
Multiprocessing systems
Considerations when designing software for a multiprocessing system
Tightly coupled memory
Memory management
Thumb-2 technology
ARM architecture profiles
ARM architecture v4T
ARM architecture v5TE
ARM architecture v6
ARM architecture v6-M
ARM architecture v7-A
ARM architecture v7-R
ARM architecture v7-M
Build options for floating-point arithmetic and linkage
Floating-point build options in ARMv6 and earlier
Floating-point build options in ARMv7 and later
Embedded Software Development
About embedded software development
Default compilation tool behavior
C library structure
Default memory map
Application startup
Tailoring the C library to your target hardware
Tailoring the image memory map to your target hardware
About the scatter-loading description syntax
Root regions
Placing the stack and heap
Run-time memory models
Scatter file with link to bit-band objects
Reset and initialization
The vector table
ROM and RAM remapping
Local memory setup considerations
Stack pointer initialization
Hardware initialization
Execution mode considerations
Target hardware and the memory map
Execute-only memory
Building applications for execute-only memory
Mixing C, C++, and Assembly Language
Instruction intrinsics, inline and embedded assembler
Access to C global variables from assembly code
Including system C header files from C++
Including your own C header files from C++
Mixed-language programming
Rules for calling between C, C++, and assembly language
Rules for calling C++ functions from C and assembly language
Information specific to C++
Calls to assembly language from C
Calls to C from assembly language
Calls to C from C++
Calls to assembly language from C++
Calls to C++ from C
Calls to C++ from assembly language
Passing a reference between C and C++
Calls to C++ from C or assembly language
Interworking ARM and Thumb
About interworking
When to use interworking
Assembly language interworking
C and C++ interworking
Pointers to functions in Thumb state
Assembly language interworking example
Interworking using veneers
C and C++ language interworking
C, C++, and assembly language interworking using veneers
Handling Processor Exceptions
About processor exceptions
Exception handling process
Types of exception in ARMv6 and earlier, ARMv7-A and ARMv7-R profiles
Vector table for ARMv6 and earlier, ARMv7-A and ARMv7-R profiles
Processor modes and registers in ARMv6 and earlier, ARMv7-A and ARMv7-R profiles
Use of System mode for exception handling
The processor response to an exception
Return from an exception handler
Reset handlers
Data Abort handler
Interrupt handlers and levels of external interrupt
Reentrant interrupt handlers
Single-channel DMA transfer
Dual-channel DMA transfer
Interrupt prioritization
Context switch
Determining the SVC to be called
Determining the instruction set state from an SVC handler
SVC handlers in assembly language
SVC handlers in C and assembly language
Using SVCs in Supervisor mode
Calling SVCs from an application
Calling SVCs dynamically from an application
Prefetch Abort handler
Undefined instruction handlers
ARMv6-M and ARMv7-M profiles
Main and Process stacks
Types of exceptions in the microcontroller profiles
Vector table for ARMv6-M and ARMv7-M profiles
Vector Table Offset Register (ARMv7-M only)
Writing the exception table for ARMv6-M and ARMv7-M profiles
The Nested Vectored Interrupt Controller
Handling an exception
Configuring the System Control Space registers
Configuring individual IRQs
Supervisor calls
System timer
Configuring SysTick
Debug Communications Channel
About the Debug Communications Channel
DCC communication between target and host debug tools
Interrupt-driven debug communications
Access from Thumb state
What is Semihosting?
What is semihosting?
The semihosting interface
Can I change the semihosting operation numbers?
Debug agent interaction SVCs
angel_SWIreason_EnterSVC (0x17)
angel_SWIreason_ReportException (0x18)
SYS_CLOSE (0x02)
SYS_CLOCK (0x10)
SYS_ELAPSED (0x30)
SYS_ERRNO (0x13)
SYS_FLEN (0x0C)
SYS_GET_CMDLINE (0x15)
SYS_HEAPINFO (0x16)
SYS_ISERROR (0x08)
SYS_ISTTY (0x09)
SYS_OPEN (0x01)
SYS_READ (0x06)
SYS_READC (0x07)
SYS_REMOVE (0x0E)
SYS_RENAME (0x0F)
SYS_SEEK (0x0A)
SYS_SYSTEM (0x12)
SYS_TICKFREQ (0x31)
SYS_TIME (0x11)
SYS_TMPNAM (0x0D)
SYS_WRITE (0x05)
SYS_WRITEC (0x03)
SYS_WRITE0 (0x04)
Software Development Guide Document Revisions
Revisions for Software Development Guide
ARM Compiler armcc User Guide
Preface
About this book
Using this book
Glossary
Typographic conventions
Feedback
Feedback on this product
Feedback on content
Other information
Overview of the Compiler
The compiler
Source language modes of the compiler
Language extensions
Language compliance
The C and C++ libraries
Getting Started with the Compiler
Compiler command-line syntax
Compiler command-line options listed by group
Default compiler behavior
Order of compiler command-line options
Using stdin to input source code to the compiler
Directing output to stdout
Filename suffixes recognized by the compiler
Compiler output files
Factors influencing how the compiler searches for header files
Compiler command-line options and search paths
Compiler search rules and the current place
The ARMCC5INC environment variable
Code compatibility between separately compiled and assembled modules
Using GCC fallback when building Linux applications
Linker feedback during compilation
Unused function code
Minimizing code size by eliminating unused functions during compilation
Compilation build time
Compilation build time
Minimizing compilation build time
Minimizing compilation build time with a single armcc invocation
Effect of --multifile on compilation build time
Minimizing compilation build time with parallel make
Compilation build time and operating system choice
Using the NEON Vectorizing Compiler
NEON technology
The NEON unit
Methods of writing code for NEON
Generating NEON instructions from C or C++ code
NEON C extensions
Automatic vectorization
Data references within a vectorizable loop
Stride patterns and data accesses
Factors affecting NEON vectorization performance
NEON vectorization performance goals
Recommended loop structure for vectorization
Data dependency conflicts when vectorizing code
Carry-around scalar variables and vectorization
Reduction of a vector to a scalar
Vectorization on loops containing pointers
Nonvectorization on loops containing pointers and indirect addressing
Nonvectorization on conditional loop exits
Vectorizable loop iteration counts
Indicating loop iteration counts to the compiler with __promise(expr)
Grouping structure accesses for vectorization
Vectorization and struct member lengths
Nonvectorization of function calls to non-inline functions from within loops
Conditional statements and efficient vectorization
Vectorization diagnostics to tune code for improved performance
Vectorizable code example
DSP vectorizable code example
What can limit or prevent automatic vectorization
Compiler Features
Compiler intrinsics
Performance benefits of compiler intrinsics
ARM assembler instruction intrinsics
Generic intrinsics
Compiler intrinsics for controlling IRQ and FIQ interrupts
Compiler intrinsics for inserting optimization barriers
Compiler intrinsics for inserting native instructions
Compiler intrinsics for Digital Signal Processing (DSP)
Compiler support for European Telecommunications Standards Institute (ETSI) basic operations
Overflow and carry status flags for C and C++ code
Texas Instruments (TI) C55x intrinsics for optimizing C code
NEON intrinsics provided by the compiler
Using NEON intrinsics
Compiler support for accessing registers using named register variables
Pragmas recognized by the compiler
Compiler and processor support for bit-banding
Compiler type attribute, __attribute__((bitband))
--bitband compiler command-line option
How the compiler handles bit-band objects placed outside bit-band regions
Compiler support for thread-local storage
Compiler support for literal pools
Compiler eight-byte alignment features
Using compiler and linker support for symbol versions
Precompiled Header (PCH) files
Automatic Precompiled Header (PCH) file processing
Precompiled Header (PCH) file processing and the header stop point
Precompiled Header (PCH) file creation requirements
Compilation with multiple Precompiled Header (PCH) files
Obsolete Precompiled Header (PCH) files
Manually specifying the filename and location of a Precompiled Header (PCH) file
Selectively applying Precompiled Header (PCH) file processing
Suppressing Precompiled Header (PCH) file processing
Message output during Precompiled Header (PCH) processing
Performance issues with Precompiled Header (PCH) files
Default compiler options that are affected by optimization level
Compiler Coding Practices
The compiler as an optimizing compiler
Compiler optimization for code size versus speed
Compiler optimization levels and the debug view
Selecting the target processor at compile time
Enabling NEON and FPU for bare-metal
Optimization of loop termination in C code
Loop unrolling in C code
Compiler optimization and the volatile keyword
Code metrics
Code metrics for measurement of code size and data size
Stack use in C and C++
Benefits of reducing debug information in objects and libraries
Methods of reducing debug information in objects and libraries
Guarding against multiple inclusion of header files
Methods of minimizing function parameter passing overhead
Returning structures from functions through registers
Functions that return the same result when called with the same arguments
Comparison of pure and impure functions
Recommendation of postfix syntax when qualifying functions with ARM function modifiers
Inline functions
Compiler decisions on function inlining
Automatic function inlining and static functions
Inline functions and removal of unused out-of-line functions at link time
Automatic function inlining and multifile compilation
Restriction on overriding compiler decisions about function inlining
Compiler modes and inline functions
Inline functions in C++ and C90 mode
Inline functions in C99 mode
Inline functions and debugging
Types of data alignment
Advantages of natural data alignment
Compiler storage of data objects by natural byte alignment
Relevance of natural data alignment at compile time
Unaligned data access in C and C++ code
The __packed qualifier and unaligned data access in C and C++ code
Unaligned fields in structures
Performance penalty associated with marking whole structures as packed
Unaligned pointers in C and C++ code
Unaligned Load Register (LDR) instructions generated by the compiler
Comparisons of an unpacked struct, a __packed struct, and a struct with individually __packed fields, and of a __packed struct and a #pragma packed struct
Compiler support for floating-point arithmetic
Default selection of hardware or software floating-point support
Example of hardware and software support differences for floating-point arithmetic
Vector Floating-Point (VFP) architectures
Limitations on hardware handling of floating-point arithmetic
Implementation of Vector Floating-Point (VFP) support code
Compiler and library support for half-precision floating-point numbers
Half-precision floating-point number format
Compiler support for floating-point computations and linkage
Types of floating-point linkage
Compiler options for floating-point linkage and computations
Floating-point linkage and computational requirements of compiler options
Processors and their implicit Floating-Point Units (FPUs)
Integer division-by-zero errors in C code
Software floating-point division-by-zero errors in C code
About trapping software floating-point division-by-zero errors
Identification of software floating-point division-by-zero errors
Software floating-point division-by-zero debugging
New language features of C99
New library features of C99
// comments in C99 and C90
Compound literals in C99
Designated initializers in C99
Hexadecimal floating-point numbers in C99
Flexible array members in C99
__func__ predefined identifier in C99
inline functions in C99
long long data type in C99 and C90
Macros with a variable number of arguments in C99
Mixed declarations and statements in C99
New block scopes for selection and iteration statements in C99
_Pragma preprocessing operator in C99
Restricted pointers in C99
Additional <math.h> library functions in C99
Complex numbers in C99
Boolean type and <stdbool.h> in C99
Extended integer types and functions in <inttypes.h> and <stdint.h> in C99
<fenv.h> floating-point environment access in C99
<stdio.h> snprintf family of functions in C99
<tgmath.h> type-generic math macros in C99
<wchar.h> wide character I/O functions in C99
How to prevent uninitialized data from being initialized to zero
Compiler Diagnostic Messages
Severity of compiler diagnostic messages
Options that change the severity of compiler diagnostic messages
Controlling compiler diagnostic messages with pragmas
Prefix letters in compiler diagnostic messages
Compiler exit status codes and termination messages
Compiler data flow warnings
Using the Inline and Embedded Assemblers of the ARM Compiler
Compiler support for inline assembly language
Inline assembler support in the compiler
Restrictions on inline assembler support in the compiler
Inline assembly language syntax with the __asm keyword in C and C++
Inline assembly language syntax with the asm keyword in C++
Inline assembler rules for compiler keywords __asm and asm
Restrictions on inline assembly operations in C and C++ code
Inline assembler register restrictions in C and C++ code
Inline assembler processor mode restrictions in C and C++ code
Inline assembler Thumb instruction set restrictions in C and C++ code
Inline assembler Vector Floating-Point (VFP) restrictions in C and C++ code
Inline assembler instruction restrictions in C and C++ code
Miscellaneous inline assembler restrictions in C and C++ code
Inline assembler and register access in C and C++ code
Inline assembler and the # constant expression specifier in C and C++ code
Inline assembler and instruction expansion in C and C++ code
Expansion of inline assembler instructions that use constants
Expansion of inline assembler load and store instructions
Inline assembler effect on processor condition flags in C and C++ code
Inline assembler expression operands in C and C++ code
Inline assembler register list operands in C and C++ code
Inline assembler intermediate operands in C and C++ code
Inline assembler function calls and branches in C and C++ code
Inline assembler branches and labels in C and C++ code
Inline assembler and virtual registers
Embedded assembler support in the compiler
Embedded assembler syntax in C and C++
Effect of compiler ARM and Thumb states on embedded assembler
Restrictions on embedded assembly language functions in C and C++ code
Compiler generation of embedded assembly language functions
Access to C and C++ compile-time constant expressions from embedded assembler
Differences between expressions in embedded assembler and C or C++
Manual overload resolution in embedded assembler
__offsetof_base keyword for related base classes in embedded assembler
Compiler-supported keywords for calling class member functions in embedded assembler
__mcall_is_virtual(D, f)
__mcall_is_in_vbase(D, f)
__mcall_offsetof_vbase(D, f)
__mcall_this_offset(D, f)
__vcall_offsetof_vfunc(D, f)
Calling nonstatic member functions in embedded assembler
Calling a nonvirtual member function
Calling a virtual member function
Accessing sp (r13), lr (r14), and pc (r15)
Differences in compiler support for inline and embedded assembly code
Compiler Command-line Options
-Aopt
--allow_fpreg_for_nonfpdata, --no_allow_fpreg_for_nonfpdata
--allow_null_this, --no_allow_null_this
--alternative_tokens, --no_alternative_tokens
--anachronisms, --no_anachronisms
--apcs=qualifier...qualifier
--arm
--arm_linux
--arm_linux_config_file=path
--arm_linux_configure
--arm_linux_paths
--arm_only
--asm
--asm_dir=directory_name
--autoinline, --no_autoinline
--bigend
--bitband
--branch_tables, --no_branch_tables
--brief_diagnostics, --no_brief_diagnostics
--bss_threshold=num
-c
-C
--c90
--c99
--code_gen, --no_code_gen
--comment_section, --no_comment_section
--common_functions, --no_common_functions
--compatible=name
--compile_all_input, --no_compile_all_input
--conditionalize, --no_conditionalize
--configure_cpp_headers=path
--configure_extra_includes=paths
--configure_extra_libraries=paths
--configure_gas=path
--configure_gcc=path
--configure_gcc_version=version
--configure_gld=path
--configure_sysroot=path
--cpp
--cpp11
--cpp_compat
--cpu=list
--cpu=name
--create_pch=filename
-Dname[(parm-list)][=def]
--data_reorder, --no_data_reorder
--debug, --no_debug
--debug_macros, --no_debug_macros
--default_definition_visibility=visibility
--default_extension=ext
--dep_name, --no_dep_name
--depend=filename
--depend_dir=directory_name
--depend_format=string
--depend_single_line, --no_depend_single_line
--depend_system_headers, --no_depend_system_headers
--depend_target=target
--diag_error=tag[,tag,...]
--diag_remark=tag[,tag,...]
--diag_style=arm|ide|gnu compiler option
--diag_suppress=tag[,tag,...]
--diag_suppress=optimizations
--diag_warning=tag[,tag,...]
--diag_warning=optimizations
--dllexport_all, --no_dllexport_all
--dllimport_runtime, --no_dllimport_runtime
--dollar, --no_dollar
--dwarf2
--dwarf3
-E
--echo
--emit_frame_directives, --no_emit_frame_directives
--enum_is_int
--errors=filename
--exceptions, --no_exceptions
--exceptions_unwind, --no_exceptions_unwind
--execstack, --no_execstack
--execute_only
--export_all_vtbl, --no_export_all_vtbl
--export_defs_implicitly, --no_export_defs_implicitly
--extended_initializers, --no_extended_initializers
--feedback=filename
--float_literal_pools, --no_float_literal_pools
--force_new_nothrow, --no_force_new_nothrow
--forceinline
--fp16_format=format
--fpmode=model
--fpu=list
--fpu=name
--friend_injection, --no_friend_injection
-g
--global_reg=reg_name[,reg_name,...]
--gnu
--gnu_defaults
--gnu_instrument, --no_gnu_instrument
--gnu_version=version
--guiding_decls, --no_guiding_decls
--help
--hide_all, --no_hide_all