ARM CoreLink DMC-520 Dynamic Memory Controller Technical Reference Manual : About this book

Product revision status

The rmpn identifier indicates the revision status of the product described in this book, for example, r1p2, where:

r`m`	Identifies the major revision of the product, for example, r1.
p`n`	Identifies the minor revision or modification status of the product, for example, p2.

Intended audience

This book is written for experienced engineers who want to integrate the delivered ARM DMC-520 product in a System on Chip (SoC) design.

Using this book

This book is organized into the following chapters:

Chapter 1 Introduction: This chapter describes the DMC-520.
Chapter 2 Functional Description: This chapter describes how the DMC-520 operates.
Chapter 3 Programmers Model: This chapter describes the programmers model of the DMC-520.
Appendix A Signal Descriptions: This appendix describes the DMC-520 signals.
Appendix B Revisions: This appendix describes the technical changes between released issues of this book.

Glossary

The ARM Glossary is a list of terms used in ARM documentation, together with definitions for those terms. The ARM Glossary does not contain terms that are industry standard unless the ARM meaning differs from the generally accepted meaning.

See the ARM Glossary for more information.

Typographic conventions

italic

Introduces special terminology, denotes cross-references, and citations.

bold

Highlights interface elements, such as menu names. Denotes signal names. Also used for terms in descriptive lists, where appropriate.

monospace

Denotes text that you can enter at the keyboard, such as commands, file and program names, and source code.

monospace

Denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full command or option name.

monospace italic

Denotes arguments to monospace text where the argument is to be replaced by a specific value.

monospace bold

Denotes language keywords when used outside example code.

<and>

Encloses replaceable terms for assembler syntax where they appear in code or code fragments. For example:

MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2>

SMALL CAPITALS

Used in body text for a few terms that have specific technical meanings, that are defined in the ARM glossary. For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and UNPREDICTABLE.

Timing diagrams

The following figure explains the components used in timing diagrams. Variations, when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams.

Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation.

Figure 1 Key to timing diagram conventions

Signals

The signal conventions are:

Signal level

The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW. Asserted means:

HIGH for active-HIGH signals.
LOW for active-LOW signals.

Lower-case n

At the start or end of a signal name denotes an active-LOW signal.

Additional reading

This book contains information that is specific to this product. See the following documents for other relevant information.

ARM publications

The following confidential books are only available to licensees:

ARM^® CoreLink™ DMC-520 Dynamic Memory Controller Design Manual (ARM 100001).
ARM^® CoreLink™ DMC-520 Dynamic Memory Controller Integration Manual (ARM 100003).
ARM^® CoreLink™ DMC-520 Dynamic Memory Controller Implementation Guide (ARM 100002).
ARM^® AMBA^® 5 CHI Protocol Specification (ARM IHI 0050).
ARM^® Low Power Interface Specification, Q-Channel and P-Channel Interfaces (ARM IHI 0068).
ARM^® AMBA^® APB Protocol Specification (ARM IHI 0024).

Other publications

JEDEC STANDARD DDR3 SDRAM Specification, JESD79-3D, http://www.jedec.org.
JEDEC STANDARD DDR3L SDRAM Specification, JESD79-3-1A, http://www.jedec.org.
JEDEC STANDARD DDR4 SDRAM Specification, JESD79-4, http://www.jedec.org.
JEDEC STANDARD DDR3 RDIMM Specification, JESD82-29, http://www.jedec.org.
JEDEC STANDARD DDR3 LRDIMM Specification, (pre-release), http://www.jedec.org.
JEDEC STANDARD DDR4 RDIMM Common Design Specification, (pre-release), http://www.jedec.org.
JEDEC STANDARD DDR4 LRDIMM Common Design Specification, (pre-release), http://www.jedec.org.
JEDEC STANDARD DDR4 RCD Specification, (pre-release), http://www.jedec.org.
JEDEC STANDARD DDR4 DB Specification, (pre-release), http://www.jedec.org.
DDR PHY Interface DFI 3.0 Specification, http://ddr-phy.org/.

Note

See the ARM^®CoreLink™ DMC-520 Dynamic Memory Controller Release Note for the actual versions of the specifications that ARM used when designing the device.

Non-Confidential	PDF version	ARM 100000_0001_00_en
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