2.3.5 Low-power Clock Control interface

This section describes the clock requirements for the DMC-520.

The DMC-520 provides a low-power control interface using the Q-channel protocol. This is used to place the DMC into its low-power state, in which state the clock can be removed. The system can use the APB interface to put the DMC into its low-power state, and take it out of its low-power state.
SDRAM provides a number of power-saving states, as distinct from those of the DMC-520:
  1. Idle-ready.
  2. Clock stop.
  3. Active power down.
  4. Precharge power down.
  5. Self-Refresh (SR).
  6. Maximum Power Down (MPD) for DDR4.
All states prohibit commands apart from Idle-ready. From states 2-6, the energy saving increases, but so does the exit latency from that state. Some SDRAMs do not support dynamic clock stopping or MPD. Specific commands, together with the clock-enable CKE signal, are used to control states 2-5. Individual CKE pins are required for each chip that requires separate power control.
The features of the DMC-520 include:
The PHY logic consumes power in standby mode. If the controller is using SDRAM low-power modes, then it indicates to the PHY that it can power down. The wake-up value that the DMC signals to the PHY with the powerdown request determines the level of power state that the PHY enters. The wake-up value is determined from a programmed value that is associated with each SDRAM power-saving state. These states are:


The DMC can also indicate that the PHY must power down in the following ways:
  • As a direct command from software, with a software-defined wake-up value.
  • As part of a Q-channel sequence, with a tie-off defined wake-up value.

Q-channel interface

The DMC has a Q-channel interface that allows an external power controller to place the DMC into a low-power state.

It is a standard Q-channel interface as defined in the ARM® Low Power Interface Specification, Q-Channel and P-Channel Interfaces using the following 4 signals.
  • qactive.
  • qreqn.
  • qacceptn.
  • qdeny.
When the DMC receives a request itl puts the DRAM into self_refresh before asserting qacceptn to accept the request that indicates the clk can be stopped.
DMC denies requests to power down using the Q-Channel when geardown_mode is enabled. In this case low-power mode can still be entered using the APB interface.
There is a separate Q-channel interface for the pclk using the following signals:
  • qactive_apb.
  • qreqn_apb.
  • qacceptn_apb.
  • qdeny_apb.
The DMC never denies a request to power down the APB clock although it might be delayed based on APB activity.


These two interfaces are interrelated and a change on one can cause qactive on the other to be asserted. If this occurs then the power up request must be responded to straight away to allow the request to be serviced.
See ARM® Low Power Interface Specification, Q-Channel and P-Channel Interfaces.
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