The DMC-520 supports DDR3 and DDR4 SDRAMs. It also supports error checking, reliability, availability, and serviceability features. In addition, Quality of Service (QoS) features and ARM TrustZone® architecture security extensions are built in throughout the controller.
The system interface provides a CHI
interface for connection to a CoreLink™
Cache Coherent Network
(CCN), an APB3 interface for configuration and initialization purposes, and an
external performance event interface for connecting to CoreSight™ on-chip debug and trace technology.
The DMC-520 has the
- Profiling signals that enable performance profiling to be performed
in the system.
- TrustZone architecture
- Buffering to optimize read and write turnaround and to maximize
- A system interface that provides:
- A CHI interface to connect to a CCN.
- An APB3 interface for configuration and initialization
- A Memory Interface (MI) that provides:
- A DFI 3.0 interface to a PHY that supports DDR3, DDR3L, and
- Low power operation through programmable SDRAM power modes.
- Reliability, Availability,
- Single Error Correcting, Double Error
Detecting (SEC-DED) ECC for off-chip DRAM.
- Symbol-based ECC, to correct memory chip and data-lane failures.
- SEC-DED ECC for on-chip RAM protection.
- Hardware Read-Modify-Write
(RMW) for systems supporting sparse writes.
- Link protection for DDR4 link errors.
- CRC write-data protection for DDR4 devices.
- A programmable mechanism for automated SDRAM scrubbing.
- Error handling.
- Refresh Control Logic for memory banks.
- Power Control Logic. This generates power down requests to the
SDRAM, and manages power enables for the PHY logic.