1.1 About the product

This is a high-level overview of the DMC-520.

The DMC-520 is an ARM® AMBA® 5 CHI SoC peripheral developed, tested, and licensed by ARM. It is a high-performance, area-optimized memory controller that is compatible with the AMBA 5 CHI protocol. It supports the following memory devices:
The following figure shows an example system.
Figure 1-1 Example system
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The DMC-520 enables data transfer between the SoC and the SDRAM devices external to the chip. It connects to the on-chip system through a single CHI interface and to a processor through the programmers APB3™ interface to program the DMC-520. It connects to the SDRAM devices through its memory interface block and the DDR PHY Interface (DFI).
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