This section lists the interfaces in the DMC-520.
The DMC-520 has the following external interfaces:
- A system interface to provide read and write access to or from a master. It uses the
- An APB3 programmers interface to program and control the DMC-520.
- A DFI3.0 compatible PHY interface to transfer data to and from the external memory.
- A profile and debug interface.
- A low-power clock control interface that uses the Q-channel protocol. See Q-channel interface.
- An abort interface that is a 4-phase request and acknowledge handshake that
you can use to recover from a livelock caused by DRAM or PHY failure.
- User I/O ports.
- A set of interrupts used to detect some operational events or handle errors for example.