2.2 Clocking and resets

The DMC-520 normally operates as one synchronous clock domain between the interconnect and the external DDR interface. However, the programming interface can operate asynchronously to this.

This section shows the clock and reset signals that the DMC-520 requires.


The following requirements, with respect to the APB and refresh controller clocks, apply:
  • clk must run synchronously with, and at the same speed as, the PHY and SDRAM and with the interfacing system interconnect.
  • pclk and clk can run asynchronously to each other.


Resets must be applied for a minimum duration of two clock cycles for each clock domain.
There is one reset per clock domain. The pclk domain must be brought out of reset prior to the clk domain.


  • To assert any DMC-520 reset signal, you must set it LOW.
  • To perform a DMC-520 reset, you must assert both reset signals.
Related reference
Wrapper topic for Signal Descriptions appendix
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