2.3.3 PHY interface
The PHY interface provides command scheduling and arbitration, including the generation of any required SDRAM prepare commands, for example, ACTIVATE and PRECHARGE. This section describes the PHY interface in the DMC-520.
The PHY interface is a DFI3.0 interface compatible with the DDR standards for DDR4 and DDR3
(including DDR3L). It provides:
- Command scheduling and arbitration, including generation of any required SDRAM
prepare commands, for example, ACTIVATE, or PRECHARGE.
- Automated AUTOREFRESH command generation.
- SDRAM interface link protection including
automated retries for failed commands to ensure the correct ordering of those retried commands to
- Automated SDRAM and PHY logic power control.
- Profile and debug information.