2.1 About the functions

This section gives a brief description of all of the functions of the device.

The following figure shows a block diagram of the functions of the DMC-520. The colors show the different categories of functions:
Figure 2-1 DMC functional block diagram
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System interface

The DMC-520 interfaces to the rest of the SoC through this interface. This is a standard CHI interface that connects to a CHI Slave Node Interface (SNF). For any attempted accesses that the system makes outside of the programmed address range of the DMC-520, the system interface responds with a non-data error response. According to how you program the DMC-520, it converts the system access information to the correct rank, bank, column, and row access of the external SDRAM that connects to it. The system interface supports TrustZone features to regulate Secure and Non-secure accesses to both Secure and Non-secure regions of memory
The DMC monitors queue occupancies and dictates whether system requests of any given QoS is to be accepted. Prefetched and Dynamic P-Credit requests are allocated based on a threshold setting, derived from register settings.

Memory channel

Through this interface the DMC-520 conducts its data transactions with the SDRAM and regulates the power consumption of the SDRAM. The DMC-520 uses the ECC information that it receives from the SDRAM to maximize the quality of information that it receives from these devices.

Programming interface

Through this interface a master in the system programs the DMC-520. You can define the Secure and Non-secure regions of external memory and also define how the DMC-520 addresses the external memory from the address that the system provides on its system interface. You can also make direct accesses to the SDRAM, for example to initialize it.

Performance monitoring unit interface

You can use the Performance Monitoring Unit (PMU) interface to monitor the performance and power settings for your specific application. This interface allows you to monitor the inner workings of the device and so enables additional information to be viewed.

QoS engine

The DMC-520 provides controls to enable you to adjust its arbitration scheme for your system to maximize the availability of your external memory devices. It provides buffers to re-order system transaction requests. It uses an advanced scheduling algorithm to ensure that traffic going to one memory bank causes minimal disruption to traffic going to a different memory bank. It also schedules transaction requests according to the availability of the destination memory bank. For system access requests to different available memory banks the DMC-520 arbitrates these requests based on the QoS priority initially then on the temporal priority. These memory access requests all compete for control of the external SDRAM bus and SDRAM bank availability.


RAS features include support for the following:
  • SECDED ECC and symbol-based ECC for external DRAM. The symbol-based ECC performs quad symbol correct and multi-symbol detect.
  • SECDED ECC of on-chip SRAM buffers within the DMC-520.
  • An automated retry of failed read transactions.
  • Write-back of corrected errors.
  • To reduce memory errors, the DMC-520 supports:
    • Link error protection for the memory interface.
    • Programmable data scrubbing where the DMC-520 periodically detects and corrects data errors in the memory itself.
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