A.1 Signals list

DMC signals list that excludes bus interface signals. The bus interface signals are defined by their own bus protocol standard.

The following table shows the Primary clock and reset signals list of the DMC.

Table A-1 DMC Primary clock and reset signals list

Signal Type Width Description
clk Input 1 Primary DMC clock
resetn Input 1 Primary DMC reset
The following table shows the APB clock and reset signals list of the DMC.

Table A-2 DMC APB clock and reset signals list

Signal Type Width Description
pclk Input 1 APB clock
presetn Input 1 APB reset
The following table shows the User I/O with APB access list of the DMC.

Table A-3 DMC User I/O with APB access list

Signal Type Width Description
user_status Input 32 User defined inputs
user_config0 Output 32 User defined outputs
user_config1 Output 32 User defined outputs
user_config2 Output 32 User defined outputs
user_config3 Output 32 User defined outputs
user_periph_id_3 Input 8 Tie-off value to set the value of CMOD in the periph_id_3 bitfield. This input is exclusive ORed with the default register value.
The following table shows the Events list of the DMC.

Table A-4 DMC Events list

Signal Type Width Description
scrub_event_in0 Input 1 Scrub event 0 trigger.
scrub_event_in1 Input 1 Scrub event 1 trigger.
scrub_event_in2 Input 1 Scrub event 2 trigger.
scrub_event_in3 Input 1 Scrub event 3 trigger.
scrub_event_in4 Input 1 Scrub event 4 trigger.
scrub_event_in5 Input 1 Scrub event 5 trigger.
scrub_event_in6 Input 1 Scrub event 6 trigger.
scrub_event_in7 Input 1 Scrub event 7 trigger.
scrub_event_out0 Output 1 Scrub event 0 triggered.
scrub_event_out1 Output 1 Scrub event 1 triggered.
scrub_event_out2 Output 1 Scrub event 2 triggered.
scrub_event_out3 Output 1 Scrub event 3 triggered.
scrub_event_out4 Output 1 Scrub event 4 triggered.
scrub_event_out5 Output 1 Scrub event 5 triggered.
scrub_event_out6 Output 1 Scrub event 6 triggered.
scrub_event_out7 Output 1 Scrub event 7 triggered.
direct_cmd_event_in0 Input 1 Direct cmd event 0 trigger.
direct_cmd_event_in1 Input 1 Direct cmd event 1 trigger.
direct_cmd_event_in2 Input 1 Direct cmd event 2 trigger.
direct_cmd_event_in3 Input 1 Direct cmd event 3 trigger.
direct_cmd_event_out0 Output 1 Direct cmd event 0 triggered.
direct_cmd_event_out1 Output 1 Direct cmd event 1 triggered.
direct_cmd_event_out2 Output 1 Direct cmd event 2 triggered.
direct_cmd_event_out3 Output 1 Direct cmd event 3 triggered.
The following table shows the Scan Signals list of the DMC.

Table A-5 DMC Scan Signals list

Signal Type Width Description
dftse Input 1 DFT scan enable
dftclkcgen Input 1 DFT clk clock gate enable
dftclkdiv2cgen Input 1 DFT clkdiv2 clock gate enable
dftpclkcgen Input 1 DFT pclk clock gate enable
dftrstdisable Input 1 DFT reset synchronizer disable
dftramhold Input 1 DFT on-chip RAM hold
dftmcphold Input 1 DFT multi-cycle path hold
The following table shows the PMU Signals list of the DMC.

Table A-6 DMC PMU Signals list

Signal Type Width Description
ev_request_valid_valid Output 1 Indicates that ev_request_valid_payload is valid
ev_request_tzfail_valid Output 1 Indicates that ev_request_tzfail_payload is valid
ev_request_retry_valid Output 1 Indicates that ev_request_retry_payload is valid
ev_retry_grant_valid Output 1 Indicates that ev_retry_grant_payload is valid
ev_request_valid_payload Output 27 A request enters the DMC
ev_request_tzfail_payload Output 22 A request fails an address translation or TrustZone permissions check
ev_request_retry_payload Output 25 A request is retried
ev_retry_grant_payload Output 15 Indicates that a P-credit has been granted.
ev_queue_fill_status_payload Output 8 Count of entries in the DMC
ev_queued_reads_payload Output 8 Count of read entries in the DMC
ev_queued_writes_payload Output 8 Count of write entries in the DMC
ev_enqueued_reads_payload Output 8 Count of read entries in the queue
ev_enqueued_writes_payload Output 8 Count of write entries in the queue
ev_arbitrated_reads_payload Output 8 Count of read entries in the arbitrated, without data state
ev_arbitrated_writes_payload Output 8 Count of write entries in the arbitrated, not clean state
ev_read_backlog_payload Output 8 Count of read entries in the backlog queue
ev_enqueue_backlog_payload Output 8 Count of entries that are waiting to get enqueued
ev_hazard_resolution_backlog_payload Output 8 Count of entries that are ready to be merged
ev_queue_allocation_backlog_payload Output 8 Count of entries that in allocation backlog
ev_enqueue_valid Output 1 Indicates that ev_enqueue_payload is valid
ev_arbitrate_valid Output 1 Indicates that ev_arbitrate_payload is valid
ev_rank_targetted_valid Output RANKS_PER_CHANNEL A rank is targeted by an enqueued entry
ev_enqueue_payload Output 34 A request is enqueued in the arbitration queue
ev_arbitrate_payload Output 12 A request is arbitrated from the arbitration queue
ev_allocate_valid Output 1 Indicates that ev_allocate_payload is valid
ev_allocate_payload Output 22 Maps sysid to allocated tag ID on entry to the DCB
ev_request_hazard_valid Output 1 Indicates that ev_request_hazard_payload is valid
ev_request_hazard_payload Output 2 A request forms a data hazard on an existing entry
ev_request_partial_valid Output 1 A request is partial (not a complete burst)
ev_request_rmw_valid Output 1 A request requires a read-modify-write
ev_ram_err_detect_valid Output 9 Indicates that ev_ram_err_detect_payload is valid
ev_ram_err_detect_payload Output 42 See ram_ecc_errd_int description
ev_ram_err_correct_valid Output 9 Indicates that ev_ram_err_correct_payload is valid
ev_ram_err_correct_payload Output 42 See ram_ecc_errc_int description
ev_dram_err_detect_valid Output 1 Indicates that ev_dram_err_detect_payload is valid
ev_dram_err_detect_payload Output 35 See dram_ecc_errd_int description
ev_dram_err_correct_valid Output 1 Indicates that ev_dram_err_correct_payload is valid
ev_dram_err_correct_payload Output 59 See dram_ecc_errc_int description
ev_turnaround_valid Output 1 Indicates that ev_rank_turnaround_payload is valid
ev_activate_valid Output 1 Indicates that ev_activate_payload is valid
ev_rdwr_valid Output 1 Indicates that ev_rdwr_payload is valid
ev_precharge_valid Output 1 Indicates that ev_precharge_payload is valid
ev_refresh_valid Output 1 Indicates that ev_refresh_payload is valid
ev_turnaround_payload Output 9 A turnaround has occurred
ev_activate_payload Output 29 An ACTIVATE command has been sent
ev_rdwr_payload Output 15 A READ/WRITE command has been sent
ev_precharge_payload Output 9 A PRECHARGE command has been sent
ev_refresh_payload Output 3 A REFRESH command has been sent
ev_pwr_state_active_valid Output MEMORY_CHIP_SELECTS The rank is active
ev_pwr_state_idle_valid Output MEMORY_CHIP_SELECTS The rank is idle
ev_pwr_state_pd_valid Output MEMORY_CHIP_SELECTS The rank is in a POWER DOWN state
ev_pwr_state_sref_valid Output MEMORY_CHIP_SELECTS The rank is in a SELF_REFRESH state
ev_bank_active_valid Output BANKS_PER_CHANNEL A bank is active (has a row open)
ev_bank_busy_valid Output BANKS_PER_CHANNEL A bank is busy (one or more timing parameters is being measured following an access)
ev_phy_update_req_valid Output 1 Indicates that ev_phy_update_req_payload is valid
ev_phy_update_valid Output 1 Indicates that ev_phy_update_payload is valid
ev_phy_update_req_payload Output 4 A PHY update request has been received (update or training)
ev_phy_update_payload Output 4 A PHY update request is in progress (update or training)
ev_phy_update_complete_valid Output 1 A PHY update request has been completed (update or training)
ev_link_err_valid Output 1 A link error has been detected
ev_tmac_limit_reached_valid Output 1 Indicates that a bank row has reached the tMAC threshold for triggering a Target Row Refresh
ev_tmaw_tracker_full_valid Output 1 Indicates that tMAC/tMAW tracking resource is full
The following table shows the Misc. signals list of the DMC.

Table A-7 DMC Misc. signals list

Signal Type Width Description
memory_type Output 3 An external output of the value of the memory_type register bitfield.
abort_req Input 1 An input to abort retries in the face of DFI link errors.
abort_ack Output 1 An output to acknowledge that the DMC has completed outstanding transactions as a result of an abort.
The following table shows the Tie-off signals list of the DMC.

Table A-8 DMC Tie-off signals list

Signal Type Width Description
t_rddata_en_diff_tie_off Input 6 Tie-off value for reset of register bitfield t_rddata_en_diff
t_phyrdcslat_tie_off Input 5 Tie-off value for reset of register bitfield t_phyrdcslat
t_phyrdlat_tie_off Input 6 Tie-off value for reset of register bitfield t_phyrdlat
t_phywrlat_diff_tie_off Input 5 Tie-off value for reset of register bitfield t_phywrlat_diff
t_phywrcslat_tie_off Input 5 Tie-off value for reset of register bitfield t_phywrcslat
t_phywrdata_tie_off Input 1 Tie-off value for reset of register bitfield t_phywrdata
refresh_dur_rdlvl_tie_off Input 1 Tie-off value for reset of register bitfield refresh_dur_rdlvl
t_rdlvl_en_tie_off Input 6 Tie-off value for reset of register bitfield t_rdlvl_en
t_rdlvl_rr_tie_off Input 10 Tie-off value for reset of register bitfield t_rdlvl_rr
refresh_dur_wrlvl_tie_off Input 1 Tie-off value for reset of register bitfield refresh_dur_wrlvl
t_wrlvl_en_tie_off Input 6 Tie-off value for reset of register bitfield t_wrlvl_en
t_wrlvl_ww_tie_off Input 10 Tie-off value for reset of register bitfield t_wrlvl_ww
t_lpresp_tie_off Input 3 Tie-off value for reset of register bitfield t_lpresp
user_config0_tie_off Input 32 Tie-off value for reset of register bitfield user_config0
user_config1_tie_off Input 32 Tie-off value for reset of register bitfield user_config1
user_config2_tie_off Input 32 Tie-off value for reset of register bitfield user_config2
user_config3_tie_off Input 32 Tie-off value for reset of register bitfield user_config3
The following table shows the Tie-off values for AMBA5 CHI list of the DMC.

Table A-9 DMC Tie-off values for AMBA5 CHI list

Signal Type Width Description
system_id Input SKY_RSP_FLIT_SRCID_WIDTHparmname> Tie-off value to set the physical node ID of the DMC
home_node_id Input (SKY_REQ_FLIT_SRCID_WIDTH*SYSTEM_REQUESTORS)parmname> Tie off value to specify the concatenated physical node IDs of up to 8 Home Nodes that are permitted to access the DMC
The following table shows the DFI Interface bus list of the DMC.

Table A-10 DMC DFI Interface list

Name Width Description
dfi_address 18 Address to DDR3 PHY
dfi_bank 3 Bank Address to PHY
dfi_ras_n 1 Row address strobe to PHY
dfi_cas_n 1 Column address strobe to PHY
dfi_we_n 1 Write enable to PHY
dfi_cs_n MEMORY_CHIP_SELECTS Chip-select to PHY
dfi_act_n 1 Activate to PHY
dfi_bg 2 Bank group address to PHY
dfi_cid 3 Chip ID to PHY
dfi_cke MEMORY_CHIP_SELECTS Clock enable to PHY
dfi_odt MEMORY_CHIP_SELECTS On Die Termination to PHY
dfi_reset_n MEMORY_CHIP_SELECTS Reset to PHY
dfi_parity_in 1 Command parity to PHY
dfi_wrdata_en (DMC_DATA_BYTES + DMC_ECC_BYTES) Write data enable PHY
dfi_wrdata (DMC_DATA_BITS + DMC_ECC_BITS) Write data to PHY
dfi_wrdata_cs_n MEMORY_CHIP_SELECTS Write Data Path Chip-select to PHY
dfi_wrdata_mask (DMC_DATA_BYTES + DMC_ECC_BYTES) Write data mask PHY
dfi_rddata_en (DMC_DATA_BYTES + DMC_ECC_BYTES) Enable for read data
dfi_rddata (DMC_DATA_BITS + DMC_ECC_BITS) Read data input from PHY
dfi_rddata_dbi_n (DMC_DATA_BYTES + DMC_ECC_BYTES) * 2 Read Data DBI. This signal is sent with dfi_rddata bus indicating DBI functionality. If not used this signal must be tied to 'b1.
dfi_rddata_valid (DMC_DATA_BYTES + DMC_ECC_BYTES) Indicates read data valid
dfi_rddata_cs_n MEMORY_CHIP_SELECTS Read Data Path Chip-select to PHY
dfi_ctrlupd_req 1 This signal is part of DFI 3.0, see JEDEC specification for more information.
dfi_ctrlupd_ack 1 This signal is part of DFI 3.0, see JEDEC specification for more information.
dfi_phyupd_req 1 DFI PHY-initiated update request
dfi_phyupd_ack 1 DFI PHY-initiated update acknowledge
dfi_phyupd_type 2 DFI PHY-initiated update type
dfi_phy_crc_mode 1 Sends CRC data as part of the data burst. 'b0 = CRC code generation and validation performed in the MC. 'b1 = CRC code generation and validation performed in the PHY.
dfi_data_byte_disable (DMC_DATA_BYTES + DMC_ECC_BYTES) This signal is part of DFI 3.0, see JEDEC specification for more information.
dfi_dram_clk_disable MEMORY_CHIP_SELECTS DRAM clock disable to PHY
dfi_init_start 1 This signal is part of DFI 3.0, see JEDEC specification for more information.
dfi_init_complete 1 Indicates PHY initialization complete
dfi_alert_n 1 This signal is part of DFI 3.0, see JEDEC specification for more information.
dfi_err 1 This signal is part of DFI 3.0, see JEDEC specification for more information.
dfi_err_info 4 This signal is part of DFI 3.0, see JEDEC specification for more information.
dfi_phylvl_req_cs_n MEMORY_CHIP_SELECTS This signal is part of DFI 3.1, see JEDEC specification for more information.
dfi_phylvl_ack_cs_n MEMORY_CHIP_SELECTS This signal is part of DFI 3.1, see JEDEC specification for more information.
dfi_rdlvl_req 1 DFI read data eye training request
dfi_rdlvl_cs_n MEMORY_CHIP_SELECTS DFI read data eye training request target chip-select
dfi_rdlvl_periodic 1 DFI read data eye training request periodic
dfi_rdlvl_en 1 DFI read data eye training enable
dfi_rdlvl_resp 1 DFI read data eye training response
dfi_rdlvl_gate_req 1 DFI read gate training request
dfi_rdlvl_gate_cs_n MEMORY_CHIP_SELECTS DFI read gate training request target chip-select
dfi_rdlvl_gate_periodic 1 DFI read gate training request periodic
dfi_rdlvl_gate_en 1 DFI read gate training enable
dfi_rdlvl_gate_resp 1 DFI read gate training response
dfi_wrlvl_req 1 DFI write leveling training request
dfi_wrlvl_cs_n MEMORY_CHIP_SELECTS DFI write leveling training request target chip-select
dfi_wrlvl_periodic 1 DFI write leveling training request periodic
dfi_wrlvl_en 1 DFI write leveling training enable
dfi_wrlvl_strobe 1 DFI write leveling training strobe
dfi_wrlvl_resp 1 DFI write leveling training response
dfi_lvl_pattern 4 This signal is part of DFI 3.0, see JEDEC specification for more information.
dfi_lvl_periodic 1 This signal is part of DFI 3.0, see JEDEC specification for more information.
dfi_lvl_cs_n MEMORY_CHIP_SELECTS This signal is part of DFI 3.0, see JEDEC specification for more information.
dfi_ref_en 1 DFI refresh during training enable
dfi_lp_ctrl_req 1 DFI command low power request
dfi_lp_data_req 1 DFI data low power request
dfi_lp_wakeup 4 DFI command low power PHY wakeup allowance
dfi_lp_ack 1 DFI command low power acknowledge
The following table shows the Q-Channel Interface for DMC bus list of the DMC.

Table A-11 DMC Q-Channel Interface for DMC list

Name Width Description
qreqn 1 Request from the external clock controller to prepare to stop the clock
qacceptn 1 Positive acknowledgment after receiving QREQn assertion indicating that the DMC has completed preparation to stop the clocks and that the external clock controller can stop the clock
qdeny 1 Negative acknowledgment after receiving QREQn assertion indicating that the DMC has refused the request from the external clock controller to prepare to stop the clock
qactive 1 Indication that the DMC is active
The following table shows the Q-Channel Interface for APB interface bus list of the DMC.

Table A-12 DMC Q-Channel Interface for APB interface list

Name Width Description
qreqn_apb 1 Request from the external clock controller to prepare to stop the clock
qacceptn_apb 1 Positive acknowledgment after receiving QREQn assertion indicating that the APB interface has completed preparation to stop the clocks and that the external clock controller can stop the clock
qdeny_apb 1 Negative acknowledgment after receiving QREQn assertion indicating that the APB interface has refused the request from the external clock controller to prepare to stop the clock
qactive_apb 1 Indication that the APB interface is active
The following table shows the Clock Frequency Change Interface bus list of the DMC.

Table A-13 DMC Clock Frequency Change Interface list

Name Width Description
cc_frequency 5 Used to indicate new frequency as part of frequency change protocol
cc_freq_change_req 1 Signals to an external clock control that the clock frequency can be updated
cc_freq_change_ack 1 Signals to the DMC from an external clock control that the clock frequency has been updated
The following table shows the Clock Frequency Change Interface bus list of the DMC.

Table A-14 DMC Clock Frequency Change Interface list

Name Width Description
dfi_frequency 5 Used to indicate new frequency as part of frequency change protocol
dfi_freq_change_req 1 Signals to an external clock control that the clock frequency can be updated
dfi_freq_change_ack 1 Signals to the DMC from an external clock control that the clock frequency has been updated
The following table shows the Memory BIST interface bus list of the DMC.

Table A-15 DMC Memory BIST interface list

Name Width Description
mbistresetn 1 MBIST reset. Active low.
mbistreq 1 MBIST request
mbistack 1 MBIST acknowledge
mbistwriteen 1 MBIST write enable
mbistreaden 1 MBIST read enable
mbistaddr 7 MBIST address
mbistarray 5 MBIST array selection
mbistindata 154 MBIST write data
mbistoutdata 154 MBIST read data
The following table shows the interrupt signal list of the DMC. All the signals are outputs from the DMC.

Table A-16 DMC interrupt list

Name Width Description
ram_ecc_errc_int 1 The DMC has detected a correctable error in an internal RAM
ram_ecc_errd_int 1 The DMC has detected an un-correctable error in an internal RAM
dram_ecc_errc_int 1 The DMC has detected a correctable error in a DRAM burst
dram_ecc_errd_int 1 The DMC has detected a data failure that could not be corrected in a DRAM burst operation
failed_access_int 1 The DMC has detected a system request that has failed a permissions check
failed_prog_int 1 The DMC has detected a programming request that is not permitted
link_err_int 1 The DRAM interface has suffered from a link failure and a recovery attempt has begun
temperature_event_int 1 The DMC has detected a temperature event signaled by the DRAM, either directly, or if a temperature delta has been observed through automated polling of the temperature sensor
arch_fsm_int 1 The DMC has detected a change in the architectural state
phy_request_int 1 The DMC has detected a PHY request
combined_int 1 A combined interrupt that is the logical OR of the other interrupts
ram_ecc_errc_oflow 1 The DMC has detected a correctable error in an internal RAM and a previously detected assertion was not cleared
ram_ecc_errd_oflow 1 The DMC has detected a un-correctable error in an internal RAM and a previously detected assertion was not cleared
dram_ecc_errc_oflow 1 The DMC has detected a correctable error in a DRAM burst and a previously detected assertion was not cleared
dram_ecc_errd_oflow 1 The DMC has detected a data failure that could not be corrected in a DRAM burst operation and a previously detected assertion was not cleared
failed_access_oflow 1 The DMC has detected a system request that has failed a permissions check and a previously detected assertion was not cleared
failed_prog_oflow 1 The DMC has detected a programming request that is not permitted and a previously detected assertion was not cleared
link_err_oflow 1 The DRAM interface has suffered from a link failure and a recovery attempt has begun and a previously detected assertion was not cleared
temperature_event_oflow 1 The DMC has detected a temperature event signaled by the DRAM, either directly, or if a temperature delta has been observed through automated polling of the temperature sensor and a previously detected assertion was not cleared
arch_fsm_oflow 1 The DMC has detected a change in the architectural state and a previously detected assertion was not cleared
phy_request_oflow 1 The DMC has detected a PHY request and a previously detected assertion was not cleared
combined_oflow 1 A combined interrupt that is the logical OR of the other interrupt overflows
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