3.3.1 memc_status

Holds the architectural status of the DMC.

The memc_status register characteristics are:
Usage constraints
Can be read from when in ALL states. Cannot be changed.
There is only one DMC configuration.
The following figure shows the bit assignments.
Figure 3-1 memc_status register bit assignments
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The following shows the bit assignments.
[31] scrub_outstanding_trans7
scrub_outstanding_trans7 bitfield.
[30] scrub_active7
scrub_active7 bitfield.
[29] scrub_outstanding_trans6
scrub_outstanding_trans6 bitfield.
[28] scrub_active6
scrub_active6 bitfield.
[27] scrub_outstanding_trans5
scrub_outstanding_trans5 bitfield.
[26] scrub_active5
scrub_active5 bitfield.
[25] scrub_outstanding_trans4
scrub_outstanding_trans4 bitfield.
[24] scrub_active4
scrub_active4 bitfield.
[23] scrub_outstanding_trans3
scrub_outstanding_trans3 bitfield.
[22] scrub_active3
scrub_active3 bitfield.
[21] scrub_outstanding_trans2
scrub_outstanding_trans2 bitfield.
[20] scrub_active2
scrub_active2 bitfield.
[19] scrub_outstanding_trans1
scrub_outstanding_trans1 bitfield.
[18] scrub_active1
scrub_active1 bitfield.
[17] scrub_outstanding_trans0
scrub_outstanding_trans0 bitfield.
[16] scrub_active0
scrub_active0 bitfield.
[15:13] Reserved_4
Unused bits
[12] geardown_status
Indicates if the DMC is operating in Geardown mode for DDR4 accesses.
[11:10] Reserved_3
Unused bits
[9] mgr_dci_failed
A direct command in a previous sequence has failed.
[8] mgr_active
mgr_active bitfield.
[7] Reserved_2
Unused bits
[6:4] dest_memc_status
The intended destination state of the DMC during an active transition, or when in the ABORTED or RECOVER state.
[3] Reserved_1
Unused bits
[2:0] memc_status
The current state of the DMC.
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