3.3.4 address_control_next

Configures the DRAM address parameters. Use the DRAM device data sheet or Serial Presence Detect (SPD)-derived values to assist in programming these values.

The address_control_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x010
Type
Read-write
Reset
0x00030202
Width
32
The following figure shows the bit assignments.
Figure 3-4 address_control_next register bit assignments
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The following shows the bit assignments.
[31:29] Reserved_5
Unused bits
[28] bank_hash_enable_next
Configures the bank hash function used in system address decode. Used to alter traffic distribution across banks.
[27:26] Reserved_4
Unused bits
[25:24] rank_bits_next
Program to match the number of active ranks to be addressed.
[23:19] Reserved_3
Unused bits
[18:16] bank_bits_next
Program to match the number of banks per chip-select (rank) on the attached DRAM device.

Note

This number corresponds to the sum total of all banks in all bank groups (where applicable) on a device.
[15:11] Reserved_2
Unused bits
[10:8] row_bits_next
Program to match the number of row bits on the attached DRAM device.
[7:3] Reserved_1
Unused bits
[2:0] column_bits_next
Program to match the number of column address bits present on the DRAM device.
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