3.3.7 low_power_control_next

Configures the low-power features of the DMC.

The low_power_control_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x020
Type
Read-write
Reset
0x00000020
Width
32
The following figure shows the bit assignments.
Figure 3-7 low_power_control_next register bit assignments
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The following shows the bit assignments.
[31:8] Reserved_2
Unused bits
[7:4] asr_period_next
Program the number of tREFI intervals to wait without activity before placing the DRAM into a self-refresh state when auto_self_refresh is enabled. The supported range for this bitfield is 1-15.
[3] auto_self_refresh_next
Program to enable or disable placing a DRAM rank into a self-refresh state when the rank has been idle for the amount of time that asr_period defines.
[2] auto_power_down_next
Program to enable or disable placing the DRAM into a power-down state when idle.
[1] stop_mem_clock_sref_next
Program to enable or disable stopping the DRAM clock when the memory device is in self-refresh, reset, or maximum power down.
[0] Reserved_1
Unused bits
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