3.3.8 turnaround_control_next

Configures the settings for arbitration between read and write and rank to rank traffic on the DRAM bus.

The turnaround_control_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x028
Type
Read-write
Reset
0x0F0F0F0F
Width
32
The following figure shows the bit assignments.
Figure 3-8 turnaround_control_next register bit assignments
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The following shows the bit assignments.
[31:30] turnaround_prescalar_next
Turnaround counter prescaler.
[29:28] Reserved_4
Unused bits
[27:24] turnaround_limit_hh_next
Program the number of turnaround prescaler periods to wait between arbitrating a turnaround in the presence of HIGH-HIGH class requests. The supported range for this bitfield is 0-15.
[23:20] Reserved_3
Unused bits
[19:16] turnaround_limit_h_next
Program the number of turnaround prescaler periods to wait between arbitrating a turnaround in the presence of HIGH class requests. The supported range for this bitfield is 0-15.
[15:12] Reserved_2
Unused bits
[11:8] turnaround_limit_m_next
Program the number of turnaround prescaler periods to wait between arbitrating a turnaround in the presence of MEDIUM class requests. The supported range for this bitfield is 0-15.
[7:4] Reserved_1
Unused bits
[3:0] turnaround_limit_l_next
Program the number of turnaround prescaler periods to wait between arbitrating a turnaround in the presence of LOW class requests. The supported range for this bitfield is 0-15.
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