3.3.9 hit_turnaround_control_next

Configures the settings for preventing starvation of non-hits in the presence of in-row hit streams.

The hit_turnaround_control_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x02C
Type
Read-write
Reset
0x08909FBF
Width
32
The following figure shows the bit assignments.
Figure 3-9 hit_turnaround_control_next register bit assignments
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The following shows the bit assignments.
[31] hits_mask_hh_next
Program to determine if DRAM row hits are prioritised over HIGH-HIGH priority traffic.
[30] Reserved_4
Unused bits
[29:24] hit_turnaround_limit_hh_next
Program the maximum number of consecutive in-row hits in the presence of HIGH-HIGH class requests. Zero disables the hit limit function. The supported range for this bitfield is 0-63.
[23] hits_mask_h_next
Program to determine if DRAM row hits are prioritised over HIGH priority traffic.
[22] Reserved_3
Unused bits
[21:16] hit_turnaround_limit_h_next
Program the maximum number of consecutive in-row hits in the presence of HIGH class requests. Zero disables the hit limit function. The supported range for this bitfield is 0-63.
[15] hits_mask_m_next
Program to determine if DRAM row hits are prioritised over MEDIUM priority traffic.
[14] Reserved_2
Unused bits
[13:8] hit_turnaround_limit_m_next
Program the maximum number of consecutive in-row hits in the presence of MEDIUM class requests. Zero disables the hit limit function. The supported range for this bitfield is 0-63.
[7] hits_mask_l_next
Program to determine if DRAM row hits are prioritised over LOW priority traffic.
[6] Reserved_1
Unused bits
[5:0] hit_turnaround_limit_l_next
Program the maximum number of consecutive in-row hits in the presence of LOW class requests. Zero disables the hit limit function. The supported range for this bitfield is 0-63.
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