3.3.18 write_priority_control_31_00_next

Configures the priority settings for write requests within the DMC

The write_priority_control_31_00_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x050
Type
Read-write
Reset
0x00000000
Width
32
The following figure shows the bit assignments.
Figure 3-18 write_priority_control_31_00_next register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The following shows the bit assignments.
[31:28] write_fill_priority_7_16ths_next
Program the priority of write requests when write requests occupy 7/16ths of the DMC queue. The supported range for this bitfield is 0-15.
[27:24] write_fill_priority_6_16ths_next
Program the priority of write requests when write requests occupy 6/16ths of the DMC queue. The supported range for this bitfield is 0-15.
[23:20] write_fill_priority_5_16ths_next
Program the priority of write requests when write requests occupy 5/16ths of the DMC queue. The supported range for this bitfield is 0-15.
[19:16] write_fill_priority_4_16ths_next
Program the priority of write requests when write requests occupy 4/16ths of the DMC queue. The supported range for this bitfield is 0-15.
[15:12] write_fill_priority_3_16ths_next
Program the priority of write requests when write requests occupy 3/16ths of the DMC queue. The supported range for this bitfield is 0-15.
[11:8] write_fill_priority_2_16ths_next
Program the priority of write requests when write requests occupy 2/16ths of the DMC queue. The supported range for this bitfield is 0-15.
[7:4] write_fill_priority_1_16ths_next
Program the priority of write requests when write requests occupy 1/16th of the DMC queue. The supported range for this bitfield is 0-15.
[3:0] Reserved_1
Unused bits
Non-ConfidentialPDF file icon PDF versionARM 100000_0001_00_en
Copyright © 2014 ARM. All rights reserved.