3.3.56 channel_status

Holds the current status of the memory channel.

The channel_status register characteristics are:
Usage constraints
Can be read from when in ALL states. Cannot be changed.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x100
Type
Read-only
Reset
0x00000003
Width
32
The following figure shows the bit assignments.
Figure 3-56 channel_status register bit assignments
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The following shows the bit assignments.
[31:30] m0_rank_mrs_mode_cs7
m0_rank_mrs_mode_cs7 bitfield.
[29:28] m0_rank_mrs_mode_cs6
m0_rank_mrs_mode_cs6 bitfield.
[27:26] m0_rank_mrs_mode_cs5
m0_rank_mrs_mode_cs5 bitfield.
[25:24] m0_rank_mrs_mode_cs4
m0_rank_mrs_mode_cs4 bitfield.
[23:22] m0_rank_mrs_mode_cs3
m0_rank_mrs_mode_cs3 bitfield.
[21:20] m0_rank_mrs_mode_cs2
m0_rank_mrs_mode_cs2 bitfield.
[19:18] m0_rank_mrs_mode_cs1
m0_rank_mrs_mode_cs1 bitfield.
[17:16] m0_rank_mrs_mode_cs0
Holds state information for this rank.
[15:8] m0_rank_sref
One-bit per rank indicating that the rank does not require the DMC to issue AUTOREFRESH commands
[7:3] Reserved_1
Unused bits
[2] m0_low_power
Indicates if all the DRAM ranks on this channel are in a state not requiring AUTOREFRESH commands
[1] m0_empty
Indicates if the interface is empty, that is, there are no outstanding requests.

Note

This value might go non-empty at any time when in the READY state.
[0] m0_idle
Indicates if the interface is idle, that is, there are no outstanding requests and no outstanding activity, including delays, associated with previous commands.

Note

This value might go non-idle at any time when in the READY state.
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