Configures the behavior of the DMC if a DRAM or PHY error is received when executing a direct command.
The dci_replay_type_next register characteristics are:
- Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
There is only one DMC configuration.
The following figure shows the bit assignments.
Figure 3-59 dci_replay_type_next register bit assignments
The following shows the bit assignments.
- [31:2] Reserved_1
- [1:0] dci_replay_type_next