3.3.59 dci_replay_type_next

Configures the behavior of the DMC if a DRAM or PHY error is received when executing a direct command.

The dci_replay_type_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x110
Type
Read-write
Reset
0x00000002
Width
32
The following figure shows the bit assignments.
Figure 3-59 dci_replay_type_next register bit assignments
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The following shows the bit assignments.
[31:2] Reserved_1
Unused bits
[1:0] dci_replay_type_next
dci_replay_type_next bitfield.
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