3.3.62 refresh_control_next

Configures the type of refresh commands issued by the DMC.

The refresh_control_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x120
Type
Read-write
Reset
0x00000000
Width
32
The following figure shows the bit assignments.
Figure 3-62 refresh_control_next register bit assignments
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The following shows the bit assignments.
[31:6] Reserved_2
Unused bits
[5:4] refresh_granularity_next
Configures the refresh rate mode of the DMC. You must program this to match the mode of the DRAM. All DRAMs requiring refresh must use the same refresh rate.
[3:0] Reserved_1
Unused bits
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