Configures the type of refresh commands issued by the DMC.
The refresh_control_next register characteristics are:
- Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
There is only one DMC configuration.
The following figure shows the bit assignments.
Figure 3-62 refresh_control_next register bit assignments
The following shows the bit assignments.
- [31:6] Reserved_2
- [5:4] refresh_granularity_next
Configures the refresh rate mode of the DMC. You must program this to match the mode of the DRAM. All DRAMs requiring refresh must use the same refresh rate.
- [3:0] Reserved_1