3.3.73 ecc_errc_count_31_00

Counter register for the DRAM ECC functionality.

The ecc_errc_count_31_00 register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x158
Type
Read-write
Reset
0x00000000
Width
32
The following figure shows the bit assignments.
Figure 3-73 ecc_errc_count_31_00 register bit assignments
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The following shows the bit assignments.
[31:24] rank3_errc_count
Corrected error count. A write to the bitfield resets the counter to the written value.
[23:16] rank2_errc_count
Corrected error count. A write to the bitfield resets the counter to the written value.
[15:8] rank1_errc_count
Corrected error count. A write to the bitfield resets the counter to the written value.
[7:0] rank0_errc_count
Corrected error count. A write to the bitfield resets the counter to the written value.
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