Counter register for the RAM ECC functionality.
The ram_err_count register characteristics are:
- Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
There is only one DMC configuration.
The following figure shows the bit assignments.
Figure 3-77 ram_err_count register bit assignments
The following shows the bit assignments.
- [31:16] ram_errd_count
Uncorrected error count. A write to the bitfield resets the counter to the written value.
- [15:0] ram_errc_count
Corrected error count. A write to this bitfield resets the counter to the written value.