Control register for DMC features.
The feature_control_next register characteristics are:
- Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
There is only one DMC configuration.
The following figure shows the bit assignments.
Figure 3-103 feature_control_next register bit assignments
The following shows the bit assignments.
- [31:29] Reserved_3
-  alert_mode_next
Configures the DMC behavior in response to dfi_alert_n being asserted.
NoteWhen performing DIMM CA training using the ALERT pin, this mode must
be set to interrupt-only mode.
- [27:20] address_mirroring_mask_next
Each bit determines if address mirroring as per the DDR3/DDR4 RDIMM Design Specification must be applied to the corresponding rank. Set to 1 to enable mirroring, 0 to disable. Normally, this bit must be set high for odd physical ranks.
-  dfi_err_mode_next
Configures the DMC behavior in response to dfi_err being asserted.
-  lvl_wakeup_en_next
Program to enable the DMC to bring a rank out of self-refresh to perform PHY training. This must not be enabled when using geardown mode.
-  mrs_output_inversion_next
Program to enable output inversion for MRS commands for DDR4 DIMMs.
-  address_mirroring_next
Program to enable address mirroring for ranks identified by address_mirroring_mask.
-  trr_enable_next
Program to enable issue of Target Row Refresh command on detection of potential maximum activate count (tMAC) violation. Must only be enabled for memories supporting this command.
-  Reserved_2
-  temp_poll_after_xsref_next
Program to insert an automatic temperature status poll command following exit from self-refresh.
- [12:9] temp_poll_after_n_ref_next
Program to insert an automatic temperature status poll command following issue of n AUTOREFRESH commands. 0 disables the functionality. 1 is RESERVED
-  zqcs_after_xsref_next
Program to insert an automatic ZQC short calibration command following exit from self-refresh.
- [7:4] zqcs_after_n_ref_next
Program to insert an automatic ZQC short calibration command following n refreshes. 0 - disables the functionality. 1 is RESERVED
-  two_t_timing_next
Program to enable or disable 2T command timing.
-  Reserved_1
-  crc_enable_next
Program to enable or disable Cyclic Redundancy Check (CRC) functionality on write data.
NoteWhen you enable CRC t_wr, t_wtr and t_wtw must be extended by one
cycle to accommodate the CRC functionality.
-  write_dbi_enable_next
Program to enable or disable Data Bus Inversion (DBI) functionality for writes.