3.3.109 t_mrr_next

Configures the tMRR timing parameter. This determines the Mode Register Read (including Multi-Purpose Register Reads) command delay before any other command is issued to the same rank. Use this value to determine the data cycles returned as a result of an MRR command.

The t_mrr_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x208
Type
Read-write
Reset
0x00000002
Width
32
The following figure shows the bit assignments.
Figure 3-109 t_mrr_next register bit assignments
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The following shows the bit assignments.
[31:9] Reserved_2
Unused bits
[8:7] Reserved_1
Unused bits
[6:0] t_mrr_next
t_mrr_next bitfield. The supported range for this bitfield is 1-127.
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