3.3.110 t_mrw_next

Configures the tMRW timing parameter. This determines the delay applied after a Mode Register Write (including Multi-Purpose Register Writes) command before any other command is issued to the same rank. Use this value for all delays associated with mode register write and set commands, so the largest of these delays must be programmed.

The t_mrw_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x20C
Type
Read-write
Reset
0x0000000C
Width
32
The following figure shows the bit assignments.
Figure 3-110 t_mrw_next register bit assignments
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The following shows the bit assignments.
[31:7] Reserved_1
Unused bits
[6:0] t_mrw_next
t_mrw_next bitfield. The supported range for this bitfield is 12-127.
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