3.3.112 t_rcd_next

Configures the tRCD timing parameter. This determines the delay applied after an ACTIVATE command before a READ or WRITE command is issued to the same bank.

The t_rcd_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x218
Type
Read-write
Reset
0x00000005
Width
32
The following figure shows the bit assignments.
Figure 3-112 t_rcd_next register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The following shows the bit assignments.
[31:5] Reserved_1
Unused bits
[4:0] t_rcd_next
t_rcd_next bitfield. The supported range for this bitfield is 4-18.
Non-ConfidentialPDF file icon PDF versionARM 100000_0001_00_en
Copyright © 2014 ARM. All rights reserved.