3.3.113 t_ras_next

Configures the tRAS timing parameter. This determines the delay applied after an ACTIVATE command before a PRECHARGE command is issued to the same bank.

The t_ras_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x21C
Type
Read-write
Reset
0x0000000E
Width
32
The following figure shows the bit assignments.
Figure 3-113 t_ras_next register bit assignments
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The following shows the bit assignments.
[31:6] Reserved_1
Unused bits
[5:0] t_ras_next
t_ras_next bitfield. The supported range for this bitfield is 8-39.
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