Configures the tRAS timing parameter. This determines the delay applied after an ACTIVATE command before a PRECHARGE command is issued to the same bank.
The t_ras_next register characteristics are:
- Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
There is only one DMC configuration.
The following figure shows the bit assignments.
Figure 3-113 t_ras_next register bit assignments
The following shows the bit assignments.
- [31:6] Reserved_1
- [5:0] t_ras_next
The supported range for this bitfield is 8-39.