3.3.116 t_rrd_next

Configures the tRRD timing parameter. This determines the delay applied after an ACTIVATE command before another ACTIVATE command is issued to the same rank. The _l and _s fields apply to the same bank group, and a different bank group, respectively, as described in the DDR4 specification.

The t_rrd_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x228
Type
Read-write
Reset
0x00000404
Width
32
The following figure shows the bit assignments.
Figure 3-116 t_rrd_next register bit assignments
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The following shows the bit assignments.
[31:20] Reserved_3
Unused bits
[19:16] t_rrd_cs_next
t_rrd_cs_next bitfield. The supported range for this bitfield is 0-15.
[15:12] Reserved_2
Unused bits
[11:8] t_rrd_l_next
t_rrd_l_next bitfield. The supported range for this bitfield is 1-15.
[7:4] Reserved_1
Unused bits
[3:0] t_rrd_s_next
t_rrd_s_next bitfield. The supported range for this bitfield is 1-15.
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