ARM CoreLink DMC-520 Dynamic Memory Controller Technical Reference Manual : 3.3.118 t_rtr

3.3.118 t_rtr_next

Configures the read-to-read timing parameter. This determines the READ to READ command delay applied between reads to the same chip, other bank group (t_rtr_s), same chip, same bank group (t_rtr_l), and different chip-selects (t_rtr_cs).

The t_rtr_next register characteristics are:

Usage constraints

Can be read from when in ALL states. Can be written to when in ALL states.

Configurations

There is only one DMC configuration.

Attributes

Offset	`0x234`
Type	Read-write
Reset	`0x00060404`
Width	32

The following figure shows the bit assignments.

Figure 3-118 t_rtr_next register bit assignments

The following shows the bit assignments.

[31:25] Reserved_4: Unused bits
[24] t_rtr_skip_next: Enable when using 2tck preamble to prevent transactions being spaced by t_rtr + 1.
[23:21] Reserved_3: Unused bits
[20:16] t_rtr_cs_next: t_rtr_cs_next bitfield. The supported range for this bitfield is 6-31.
[15:13] Reserved_2: Unused bits
[12:8] t_rtr_l_next: t_rtr_l_next bitfield. The supported range for this bitfield is 4-31.
[7:5] Reserved_1: Unused bits
[4:0] t_rtr_s_next: t_rtr_s_next bitfield. The supported range for this bitfield is 4-31.

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