3.3.119 t_rtw_next

Configures the read-to-write timing parameter. This determines the READ to WRITE command delay applied between issued commands to the same chip, other bank group (t_rtw_s), same chip, same bank group (t_trw_l), and other chip-selects (t_rtw_cs).

The t_rtw_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x238
Type
Read-write
Reset
0x00060606
Width
32
The following figure shows the bit assignments.
Figure 3-119 t_rtw_next register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The following shows the bit assignments.
[31:21] Reserved_3
Unused bits
[20:16] t_rtw_cs_next
t_rtw_cs_next bitfield. The supported range for this bitfield is 4-31.
[15:13] Reserved_2
Unused bits
[12:8] t_rtw_l_next
t_rtw_l_next bitfield. The supported range for this bitfield is 4-31.
[7:5] Reserved_1
Unused bits
[4:0] t_rtw_s_next
t_rtw_s_next bitfield. The supported range for this bitfield is 4-31.
Non-ConfidentialPDF file icon PDF versionARM 100000_0001_00_en
Copyright © 2014 ARM. All rights reserved.