3.3.121 t_wr_next

Configures the tWR timing parameter. This determines the write recovery time and is used as the delay applied between the issue of a WRITE command and subsequent commands, other than WRITEs, to the same bank. This must take into account CRC timing requirements.

The t_wr_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x244
Type
Read-write
Reset
0x00000005
Width
32
The following figure shows the bit assignments.
Figure 3-121 t_wr_next register bit assignments
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The following shows the bit assignments.
[31:6] Reserved_1
Unused bits
[5:0] t_wr_next
t_wr_next bitfield. The supported range for this bitfield is 5-63.
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