3.3.123 t_wtw_next

Configures the write-to-write timing parameter for same chip, other bank group (t_wtw_s), same chip, same bank group (t_wtw_l), alternate chip (t_wtw_cs) writes. These must take into account CRC timing requirements.

The t_wtw_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x24C
Type
Read-write
Reset
0x00060404
Width
32
The following figure shows the bit assignments.
Figure 3-123 t_wtw_next register bit assignments
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The following shows the bit assignments.
[31:25] Reserved_4
Unused bits
[24] t_wtw_skip_next
Enable when using 2tck preamble to prevent transactions being spaced by t_wtw + 1.
[23:22] Reserved_3
Unused bits
[21:16] t_wtw_cs_next
t_wtw_cs_next bitfield. The supported range for this bitfield is 6-35.
[15:14] Reserved_2
Unused bits
[13:8] t_wtw_l_next
t_wtw_l_next bitfield. The supported range for this bitfield is 4-35.
[7:6] Reserved_1
Unused bits
[5:0] t_wtw_s_next
t_wtw_s_next bitfield. The supported range for this bitfield is 4-35.
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