3.3.130 t_ckxsr_next

Configures the delay between DRAM clock enable and exiting self-refresh. This parameter is applied when re-instating the clock when in self-refresh and when in a maximum power-down state.

The t_ckxsr_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x26C
Type
Read-write
Reset
0x00000001
Width
32
The following figure shows the bit assignments.
Figure 3-130 t_ckxsr_next register bit assignments
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The following shows the bit assignments.
[31:5] Reserved_1
Unused bits
[4:0] t_ckxsr_next
t_ckxsr_next bitfield. The supported range for this bitfield is 1-31.
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