Configures the delay between DRAM clock enable and exiting self-refresh. This parameter is applied when re-instating the clock when in self-refresh and when in a maximum power-down state.
The t_ckxsr_next register characteristics are:
- Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
There is only one DMC configuration.
The following figure shows the bit assignments.
Figure 3-130 t_ckxsr_next register bit assignments
The following shows the bit assignments.
- [31:5] Reserved_1
- [4:0] t_ckxsr_next
The supported range for this bitfield is 1-31.