3.3.131 t_cmd_next

Configures command signalling timing.

The t_cmd_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x270
Type
Read-write
Reset
0x00000000
Width
32
The following figure shows the bit assignments.
Figure 3-131 t_cmd_next register bit assignments
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The following shows the bit assignments.
[31:12] Reserved_2
Unused bits
[11:8] t_cal_next
Specifies the Command Address latency at the DDR4 device. The supported range for this bitfield is 0-10.

Note

t_cal must be zero when you use RDIMMs.
[7:4] Reserved_1
Unused bits
[3:0] t_cmd_lat_next
Specifies the number of DFI clocks after the dfi_cs_n signal is asserted until the associated command and address bus is driven. The supported range for this bitfield is 0-10.
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