Parity latencies t_parinlat and t_completion.
The t_parity_next register characteristics are:
- Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
There is only one DMC configuration.
The following figure shows the bit assignments.
Figure 3-132 t_parity_next register bit assignments
The following shows the bit assignments.
- [31:14] Reserved_2
- [13:8] t_completion_next
Determines the DMC clock cycle delay between when the dfi_cs_n signal is asserted and the cycle in which that command can be considered complete. In programming this value, you must consider the DFI timing parameters t_wrdata_delay, t_error_resp, t_crcmax_lat, and t_phyrdlatmax to ensure all have expired, where applicable, within t_completion cycles. The supported range for this bitfield is 9-60.
- [7:2] Reserved_1
- [1:0] t_parin_lat_next
Specifies the number of DFI clocks between when the dfi_cs_n signal is asserted and when the associated dfi_parity_in signal is driven. The supported range for this bitfield is 0-3.