3.3.134 t_rddata_en_next

Determines the time between a READ command commencing on the DFI interface, and the assertion of the dfi_read_en signal.

The t_rddata_en_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x300
Type
Read-write
Reset
0x00000001
Width
32
The following figure shows the bit assignments.
Figure 3-134 t_rddata_en_next register bit assignments
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The following shows the bit assignments.
[31:21] Reserved_3
Unused bits
[20:16] t_phyrdcslat_next
Specifies the number of DFI PHY clocks between a READ command commencing on the DFI interface (assertion of chip-select), and when the associated dfi_rddata_cs_n signal is asserted. The supported range for this bitfield is 0-31.
[15:14] Reserved_2
Unused bits
[13:8] t_rddata_en_diff_next
Describes a PHY specific value useful for aligning t_rddata_en for a specific PHY. This value has no effect on the controller. The supported range for this bitfield is 0-40.
[7:6] Reserved_1
Unused bits
[5:0] t_rddata_en_next
t_rddata_en_next bitfield. The supported range for this bitfield is 0-40.
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