Determines the time between a READ command commencing on the DFI interface, and the assertion of the dfi_read_en signal.
The t_rddata_en_next register characteristics are:
- Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
There is only one DMC configuration.
The following figure shows the bit assignments.
Figure 3-134 t_rddata_en_next register bit assignments
The following shows the bit assignments.
- [31:21] Reserved_3
- [20:16] t_phyrdcslat_next
Specifies the number of DFI PHY clocks between a READ command commencing on the DFI interface (assertion of chip-select), and when the associated dfi_rddata_cs_n signal is asserted. The supported range for this bitfield is 0-31.
- [15:14] Reserved_2
- [13:8] t_rddata_en_diff_next
Describes a PHY specific value useful for aligning t_rddata_en for a specific PHY. This value has no effect on the controller. The supported range for this bitfield is 0-40.
- [7:6] Reserved_1
- [5:0] t_rddata_en_next
The supported range for this bitfield is 0-40.