The t_phyrdlat_next register characteristics are:
- Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
- Configurations
There is only one DMC configuration.
- Attributes
| Offset | 0x304
|
| Type | Read-write
|
| Reset | 0x00000000
|
| Width | 32
|
The following figure shows the bit assignments.
Figure 3-135 t_phyrdlat_next register bit assignments
The following shows the bit assignments.
- [31:6] Reserved_1
Unused bits
- [5:0] t_phyrdlat_next
Determines the maximum time between the assertion of the dfi_read_en signal and the assertion of the dfi_rddata_valid signal by the PHY. The supported range for this bitfield is 2-62.
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