3.3.137 rdlvl_control_next

Determines the DMC behavior during read training operations. See the PHY training interface section of the Integration Manual for more details on PHY training.

The rdlvl_control_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
There is only one DMC configuration.
The following figure shows the bit assignments.
Figure 3-137 rdlvl_control_next register bit assignments
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The following shows the bit assignments.
[31:25] Reserved_7
Unused bits
[24] rdlvl_preamble_next
For DDR4 program to enable or disable issue of preamble training mode MRS prior to performing read leveling training.
[23:20] Reserved_6
Unused bits
[19:16] rdlvl_pattern_next
Program the value to be driven onto dfi_lvl_pattern during training. The DMC ignores the value. For default DFI encodings see the DFI specification [5].
[15] Reserved_5
Unused bits
[14] rdlvl_err_en_next
If enabled replay commands because of dfi_err during training.
[13] refresh_dur_rdlvl_next
Program to enable AUTOREFRESH commands to be generated during training operations. When enabled (1'b1), the DMC exits a training sequence to perform refresh.
[12] rdlvl_refresh_next
Program to enable or disable issue of an AUTOREFRESH command prior to performing read leveling training.
[11] Reserved_4
Unused bits
[10:9] rdlvl_command_ba1_0_next
Program the BA address to use for training commands.
[8] Reserved_3
Unused bits
[7:5] Reserved_2
Unused bits
[4] rdlvl_setup_next
Program the command that sets up the DRAM for read leveling training.
[3:1] Reserved_1
Unused bits
[0] rdlvl_mode_next
Program the mode used for read leveling training.
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