3.3.138 rdlvl_mrs_next

Determines the Mode Register command to use to place the DRAM into a training mode for read training, when enabled by the rdlvl_control register. See the PHY interface section of the Integration Manual for more information on PHY training.

The rdlvl_mrs_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x314
Type
Read-write
Reset
0x00000004
Width
32
The following figure shows the bit assignments.
Figure 3-138 rdlvl_mrs_next register bit assignments
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The following shows the bit assignments.
[31:13] Reserved_1
Unused bits
[12:0] rdlvl_mrs_next
Program the Mode Register command the DMC uses to place the DRAM into training mode. Set address bits [2:0] for the Mode Register write to MR3.
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