3.3.139 t_rdlvl_en_next

Configures the t_rdlvl_en timing parameter. This specifies the cycle delay between asserting dfi_rdlvl_en and the first training command, and also the cycle delay between deasserting dfi_rdlvl_en and performing any subsequent command. It also specifies the minimum delay between training commands and refreshes during training.

The t_rdlvl_en_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x318
Type
Read-write
Reset
0x00000000
Width
32
The following figure shows the bit assignments.
Figure 3-139 t_rdlvl_en_next register bit assignments
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The following shows the bit assignments.
[31:6] Reserved_1
Unused bits
[5:0] t_rdlvl_en_next
t_rdlvl_en_next bitfield. The supported range for this bitfield is 1-63.
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