3.3.141 wrlvl_control_next

Determines the DMC behavior during write training operations. See the PHY training interface section of the Integration Manual for more information on PHY training.

The wrlvl_control_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x320
Type
Read-write
Reset
0x00001000
Width
32
The following figure shows the bit assignments.
Figure 3-141 wrlvl_control_next register bit assignments
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The following shows the bit assignments.
[31:20] Reserved_7
Unused bits
[19:16] wrlvl_pattern_next
Program the value to be driven onto dfi_lvl_pattern during training. The DMC ignores the value. For default DFI encodings see the DFI specification [5]. The supported range for this bitfield is 0-15.
[15] Reserved_6
Unused bits
[14] wrlvl_err_en_next
If enabled replay commands because of dfi_err during training.
[13] refresh_dur_wrlvl_next
Program to enable AUTOREFRESH commands to be generated during training operations. When enabled (1'b1), the DMC exits a training sequence to perform refresh.
[12] wrlvl_refresh_next
Program to enable or disable issue of an AUTOREFRESH command prior to performing write leveling training.
[11] Reserved_5
Unused bits
[10:9] Reserved_4
Unused bits
[8] Reserved_3
Unused bits
[7:5] Reserved_2
Unused bits
[4] wrlvl_setup_next
Program the command that sets up the DRAM for write leveling training.
[3:1] Reserved_1
Unused bits
[0] wrlvl_mode_next
Program the mode used for write leveling training.
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