3.3.142 wrlvl_mrs_next

Determines the Mode Register command that the DMC must use to put the DRAM into a training mode for write levelling. You enable this function with the wrlvl_control Register. See the PHY training interface section of the Integration Manual for more information.

The wrlvl_mrs_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x324
Type
Read-write
Reset
0x00000086
Width
32
The following figure shows the bit assignments.
Figure 3-142 wrlvl_mrs_next register bit assignments
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The following shows the bit assignments.
[31:13] Reserved_1
Unused bits
[12:0] wrlvl_mrs_next
Program the command the DMC uses to place the DRAM into training mode. Set address bits [12:0] for the Mode Register write to MR1.
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