Configures the t_wrlvl_ww timing parameter. Specifies the cycle delay between training commands. Also specifies the minimum delay between the last training command and de-asserting dfi_wrlvl_en on observing dfi_wrlvl_resp.
The t_wrlvl_ww_next register characteristics are:
- Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
There is only one DMC configuration.
The following figure shows the bit assignments.
Figure 3-144 t_wrlvl_ww_next register bit assignments
The following shows the bit assignments.
- [31:10] Reserved_1
- [9:0] t_wrlvl_ww_next
The supported range for this bitfield is 1-1023.