3.3.144 t_wrlvl_ww_next

Configures the t_wrlvl_ww timing parameter. Specifies the cycle delay between training commands. Also specifies the minimum delay between the last training command and de-asserting dfi_wrlvl_en on observing dfi_wrlvl_resp.

The t_wrlvl_ww_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x32C
Type
Read-write
Reset
0x00000000
Width
32
The following figure shows the bit assignments.
Figure 3-144 t_wrlvl_ww_next register bit assignments
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The following shows the bit assignments.
[31:10] Reserved_1
Unused bits
[9:0] t_wrlvl_ww_next
t_wrlvl_ww_next bitfield. The supported range for this bitfield is 1-1023.
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