3.3.145 phy_power_control_next

Configures the low-power requests made to the PHY for the different channel states.

The phy_power_control_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x348
Type
Read-write
Reset
0x00000000
Width
32
The following figure shows the bit assignments.
Figure 3-145 phy_power_control_next register bit assignments
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The following shows the bit assignments.
[31:28] Reserved_2
Unused bits
[27:24] lp_wakeup_arch_next
Program the PHY wakeup encoding for PHY low-power requests when entering LOW-POWER architectural state. The supported range for this bitfield is 0-15.
[23:20] lp_wakeup_mpd_next
Program the PHY wakeup encoding for PHY low-power requests when in MPD. The supported range for this bitfield is 0-15.
[19:16] lp_wakeup_sref_next
Program the PHY wakeup encoding for PHY low-power requests when in self-refresh. The supported range for this bitfield is 0-15.
[15:12] lp_wakeup_pd_next
Program the PHY wakeup encoding for PHY low-power requests when powered down. The supported range for this bitfield is 0-15.
[11:8] lp_wakeup_idle_next
Program the PHY wakeup encoding for PHY low-power requests when idle. The supported range for this bitfield is 0-15.
[7:5] Reserved_1
Unused bits
[4] lp_arch_en_next
Program to enable or disable a PHY low-power request when entering LOW-POWER architectural state.
[3] lp_mpd_en_next
Program to enable or disable a PHY low-power request when in MPD.
[2] lp_sref_en_next
Program to enable or disable a PHY low-power request when in self-refresh.
[1] lp_pd_en_next
Program to enable or disable a PHY low-power request when in power down.
[0] lp_idle_en_next
Program to enable or disable a PHY low-power request when idle.
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