3.3.146 t_lpresp_next

Configures the minimum cycle delay to apply for PHY low-power handshakes.

The t_lpresp_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x34C
Type
Read-write
Reset
0x00000000
Width
32
The following figure shows the bit assignments.
Figure 3-146 t_lpresp_next register bit assignments
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The following shows the bit assignments.
[31:3] Reserved_1
Unused bits
[2:0] t_lpresp_next
The DMC waits a minimum t_lpresp cycles after asserting a PHY low power request before deasserting the request and resuming other commands. Zero means wait for dfi_lp_ack. The supported range for this bitfield is 0-7.
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