The phy_update_control_next register characteristics are:
- Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
- Configurations
There is only one DMC configuration.
- Attributes
| Offset | 0x350
|
| Type | Read-write
|
| Reset | 0x0FE00000
|
| Width | 32
|
The following figure shows the bit assignments.
Figure 3-147 phy_update_control_next register bit assignments
The following shows the bit assignments.
- [31:29] Reserved_5
Unused bits
- [28] phyupd_mode_next
Configures the DMC behavior in response to dfi_phyupd_req being asserted.
- [27:21] t_ctrlupd_min_next
Sets the number of cycles the DMC waits for acknowledgment of a cltrupd_req before deasserting the request and continuing normal operation. A value of 0x0 indicates the DMC must always wait for an acknowledgment before proceeding. The supported range for this bitfield is 0-127.
- [20] ctrlupd_after_xsref_next
Program to enable an automatic DMC-initiated PHY update request after exiting self-refresh
- [19:16] ctrlupd_after_n_ref_next
Program to enable an automatic DMC-initiated PHY update request after every n AUTOREFRESH commands. Zero disables the functionality. One is RESERVED
- [15:14] Reserved_4
Unused bits
- [13:12] phyupd_type_11_next
Program the required response to PHY update requests of type 11.
- [11:10] Reserved_3
Unused bits
- [9:8] phyupd_type_10_next
Program the required response to PHY update requests of type 10.
- [7:6] Reserved_2
Unused bits
- [5:4] phyupd_type_01_next
Program the required response to PHY update requests of type 01.
- [3:2] Reserved_1
Unused bits
- [1:0] phyupd_type_00_next
Program the required response to PHY update requests of type 00.
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