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ARM® CoreLink™ DMC-520 Dynamic Memory Controller Technical Reference ManualRevision r0p1
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3.3.148 odt_timing_next

Configures the ODT on and off timing.

The odt_timing_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x358
Type
Read-write
Reset
0x06000600
Width
32
The following figure shows the bit assignments.
Figure 3-148 odt_timing_next register bit assignments
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The following shows the bit assignments.
[31:29] Reserved_4
Unused bits
[28:24] t_odt_off_rd_next
Time from cs assertion to ODT being deasserted for read. The supported range for this bitfield is 2-31.
[23:21] Reserved_3
Unused bits
[20:16] t_odt_on_rd_next
Time from cs assertion to ODT being asserted for read. The supported range for this bitfield is 0-29.
[15:13] Reserved_2
Unused bits
[12:8] t_odt_off_wr_next
Time from cs assertion to ODT being deasserted for write. The supported range for this bitfield is 2-31.
[7:5] Reserved_1
Unused bits
[4:0] t_odt_on_wr_next
Time from cs assertion to ODT being asserted for write. The supported range for this bitfield is 0-29.
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