3.3.149 odt_wr_control_31_00_next

Configures the ODT on and off settings for active and inactive ranks during writes.

The odt_wr_control_31_00_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x360
Type
Read-write
Reset
0x08040201
Width
32
The following figure shows the bit assignments.
Figure 3-149 odt_wr_control_31_00_next register bit assignments
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The following shows the bit assignments.
[31:24] odt_mask_wr_cs3_next
Drives the dfi_odt[7:0] output signal during a write to DRAM rank 3. The supported range for this bitfield is 0-255.
[23:16] odt_mask_wr_cs2_next
Drives the dfi_odt[7:0] output signal during a write to DRAM rank 2. The supported range for this bitfield is 0-255.
[15:8] odt_mask_wr_cs1_next
Drives the dfi_odt[7:0] output signal during a write to DRAM rank 1. The supported range for this bitfield is 0-255.
[7:0] odt_mask_wr_cs0_next
Drives the dfi_odt[7:0] output signal during a write to DRAM rank 0. The supported range for this bitfield is 0-255.
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