3.3.152 odt_rd_control_63_32_next

Configures the ODT on and off settings for active and inactive ranks during reads.

The odt_rd_control_63_32_next register characteristics are:
Usage constraints
Can be read from when in ALL states. Can be written to when in ALL states.
Configurations
There is only one DMC configuration.
Attributes
Offset
0x36C
Type
Read-write
Reset
0x00000000
Width
32
The following figure shows the bit assignments.
Figure 3-152 odt_rd_control_63_32_next register bit assignments
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The following shows the bit assignments.
[31:24] odt_mask_rd_cs7_next
Drives the dfi_odt[7:0] output signal during a read to DRAM rank 7. The supported range for this bitfield is 0-255.
[23:16] odt_mask_rd_cs6_next
Drives the dfi_odt[7:0] output signal during a read to DRAM rank 6. The supported range for this bitfield is 0-255.
[15:8] odt_mask_rd_cs5_next
Drives the dfi_odt[7:0] output signal during a read to DRAM rank 5. The supported range for this bitfield is 0-255.
[7:0] odt_mask_rd_cs4_next
Drives the dfi_odt[7:0] output signal during a read to DRAM rank 4. The supported range for this bitfield is 0-255.
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